DE69224727T2 - Schaltung mit eingebautem Selbsttest - Google Patents

Schaltung mit eingebautem Selbsttest

Info

Publication number
DE69224727T2
DE69224727T2 DE69224727T DE69224727T DE69224727T2 DE 69224727 T2 DE69224727 T2 DE 69224727T2 DE 69224727 T DE69224727 T DE 69224727T DE 69224727 T DE69224727 T DE 69224727T DE 69224727 T2 DE69224727 T2 DE 69224727T2
Authority
DE
Germany
Prior art keywords
functional block
outputs
output
built
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224727T
Other languages
English (en)
Other versions
DE69224727D1 (de
Inventor
Takeshi Ikenaga
Jun-Ichi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3332300A external-priority patent/JP2719547B2/ja
Priority claimed from JP4083201A external-priority patent/JP2711492B2/ja
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE69224727D1 publication Critical patent/DE69224727D1/de
Application granted granted Critical
Publication of DE69224727T2 publication Critical patent/DE69224727T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/83Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures
DE69224727T 1991-12-16 1992-12-15 Schaltung mit eingebautem Selbsttest Expired - Fee Related DE69224727T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3332300A JP2719547B2 (ja) 1991-12-16 1991-12-16 疑似乱数パターン発生器
JP4083201A JP2711492B2 (ja) 1992-03-05 1992-03-05 組込み自己試験回路

Publications (2)

Publication Number Publication Date
DE69224727D1 DE69224727D1 (de) 1998-04-16
DE69224727T2 true DE69224727T2 (de) 1998-11-12

Family

ID=26424262

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224727T Expired - Fee Related DE69224727T2 (de) 1991-12-16 1992-12-15 Schaltung mit eingebautem Selbsttest

Country Status (3)

Country Link
US (1) US5301199A (de)
EP (1) EP0549949B1 (de)
DE (1) DE69224727T2 (de)

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US5978946A (en) * 1997-10-31 1999-11-02 Intel Coporation Methods and apparatus for system testing of processors and computers using signature analysis
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US6229465B1 (en) 1999-04-30 2001-05-08 International Business Machines Corporation Built in self test method and structure for analog to digital converter
US6874109B1 (en) 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
EP1242885B1 (de) * 1999-11-23 2009-10-07 Mentor Graphics Corporation Ständige anwendung und dekompression von prüfmustern zu einer zu testenden integrierten schaltung
US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
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US6353842B1 (en) 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
US8533547B2 (en) 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US7493540B1 (en) 1999-11-23 2009-02-17 Jansuz Rajski Continuous application and decompression of test patterns to a circuit-under-test
US6675336B1 (en) * 2000-06-13 2004-01-06 Cypress Semiconductor Corp. Distributed test architecture for multiport RAMs or other circuitry
US6789220B1 (en) * 2001-05-03 2004-09-07 Xilinx, Inc. Method and apparatus for vector processing
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US8166361B2 (en) 2001-09-28 2012-04-24 Rambus Inc. Integrated circuit testing module configured for set-up and hold time testing
US8001439B2 (en) * 2001-09-28 2011-08-16 Rambus Inc. Integrated circuit testing module including signal shaping interface
US8286046B2 (en) 2001-09-28 2012-10-09 Rambus Inc. Integrated circuit testing module including signal shaping interface
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US6782518B2 (en) 2002-03-28 2004-08-24 International Business Machines Corporation System and method for facilitating coverage feedback testcase generation reproducibility
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US7509550B2 (en) 2003-02-13 2009-03-24 Janusz Rajski Fault diagnosis of compressed test responses
EP1978446B1 (de) * 2003-02-13 2011-11-02 Mentor Graphics Corporation Komprimieren von Testantworten unter Verwendung eines Kompaktors
US7437640B2 (en) * 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7302624B2 (en) 2003-02-13 2007-11-27 Janusz Rajski Adaptive fault diagnosis of compressed test responses
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US7260760B2 (en) * 2005-04-27 2007-08-21 International Business Machines Corporation Method and apparatus to disable compaction of test responses in deterministic test-set embedding-based BIST
JP2007101395A (ja) * 2005-10-05 2007-04-19 Sony Corp 回路装置の検査装置、検査方法及び製造方法
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US9268660B2 (en) 2014-03-12 2016-02-23 International Business Machines Corporation Matrix and compression-based error detection
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Also Published As

Publication number Publication date
EP0549949B1 (de) 1998-03-11
US5301199A (en) 1994-04-05
EP0549949A2 (de) 1993-07-07
DE69224727D1 (de) 1998-04-16
EP0549949A3 (en) 1994-06-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee