DE602004028794D1 - Leiterplatte - Google Patents

Leiterplatte

Info

Publication number
DE602004028794D1
DE602004028794D1 DE602004028794T DE602004028794T DE602004028794D1 DE 602004028794 D1 DE602004028794 D1 DE 602004028794D1 DE 602004028794 T DE602004028794 T DE 602004028794T DE 602004028794 T DE602004028794 T DE 602004028794T DE 602004028794 D1 DE602004028794 D1 DE 602004028794D1
Authority
DE
Germany
Prior art keywords
circuit board
board
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004028794T
Other languages
English (en)
Inventor
Yasuto Ishimaru
Kensuke Nishi
Hiroshi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of DE602004028794D1 publication Critical patent/DE602004028794D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
DE602004028794T 2003-12-16 2004-12-14 Leiterplatte Active DE602004028794D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003418161A JP4133786B2 (ja) 2003-12-16 2003-12-16 配線回路基板

Publications (1)

Publication Number Publication Date
DE602004028794D1 true DE602004028794D1 (de) 2010-10-07

Family

ID=34510619

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004028794T Active DE602004028794D1 (de) 2003-12-16 2004-12-14 Leiterplatte

Country Status (7)

Country Link
US (1) US7087844B2 (de)
EP (1) EP1545170B1 (de)
JP (1) JP4133786B2 (de)
KR (1) KR101088330B1 (de)
CN (1) CN100397624C (de)
DE (1) DE602004028794D1 (de)
TW (1) TWI346378B (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4399337B2 (ja) * 2004-09-13 2010-01-13 株式会社フューチャービジョン 平面パターンを有する基板およびそれを用いた表示装置
JP4284544B2 (ja) * 2005-06-29 2009-06-24 セイコーエプソン株式会社 半導体装置及びその製造方法
JP4786976B2 (ja) * 2005-09-13 2011-10-05 パナソニック株式会社 配線基板及びその製造方法、並びに半導体装置
KR100726458B1 (ko) * 2006-01-16 2007-06-11 삼성전자주식회사 기판조립체
US7394164B2 (en) * 2006-07-28 2008-07-01 Ultra Chip, Inc. Semiconductor device having bumps in a same row for staggered probing
US7732930B2 (en) * 2006-09-06 2010-06-08 Kabushiki Kaisha Toshiba Semiconductor device, relay chip, and method for producing relay chip
JP4790558B2 (ja) * 2006-10-02 2011-10-12 日東電工株式会社 配線回路基板の製造方法
JPWO2008059571A1 (ja) * 2006-11-15 2010-02-25 パナソニック株式会社 回路基板の接続構造および回路基板
JP5001731B2 (ja) * 2007-07-02 2012-08-15 日東電工株式会社 配線回路基板と電子部品との接続構造
JP4352279B2 (ja) * 2007-08-21 2009-10-28 セイコーエプソン株式会社 半導体装置及びその製造方法
JP2009094361A (ja) * 2007-10-10 2009-04-30 Nitto Denko Corp Ｃｏｆ基板
DE102008020306A1 (de) 2008-04-23 2009-10-29 Dr. Ing. H.C. F. Porsche Aktiengesellschaft Durchgangselement
JP5375182B2 (ja) * 2009-02-26 2013-12-25 富士通株式会社 フレキシブルプリント基板
JP2011203061A (ja) * 2010-03-25 2011-10-13 Toshiba Corp パターン計測方法およびパターン計測装置
TWI431740B (zh) * 2010-10-21 2014-03-21 E Ink Holdings Inc 電極陣列
KR102051122B1 (ko) 2013-06-18 2019-12-02 삼성전자주식회사 표시 장치
CN109068967B (zh) * 2016-05-10 2020-12-25 奥林巴斯株式会社 电子电路单元、摄像单元、摄像模块以及内窥镜
US10263352B2 (en) 2016-06-10 2019-04-16 Te Connectivity Corporation Electrical contact pad for electrically contacting a connector
US10128597B2 (en) * 2016-06-10 2018-11-13 Te Connectivity Corporation Electrical contact pad for electrically contacting a connector
US10320099B2 (en) 2016-06-10 2019-06-11 Te Connectivity Corporation Connector with asymmetric base section
US11545495B2 (en) * 2017-06-29 2023-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM
US9997868B1 (en) 2017-07-24 2018-06-12 Te Connectivity Corporation Electrical connector with improved impedance characteristics
CN107918581A (zh) * 2017-11-09 2018-04-17 郑州云海信息技术有限公司 一种针对高速信号连接器优化分析方法与系统
CN113692114B (zh) * 2021-08-31 2023-04-28 联想(北京)有限公司 电路板及其制作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199228A (en) * 1981-06-02 1982-12-07 Toshiba Corp Wire bonding pad device
JPS5980957A (ja) * 1982-10-29 1984-05-10 Matsushita Electronics Corp 半導体装置
JPS6334997A (ja) * 1986-07-29 1988-02-15 三菱電機株式会社 外部取出し端子パタ−ン
JPH0242737A (ja) * 1989-06-08 1990-02-13 Toshiba Corp ワイヤボンディングパッド装置
JPH04243156A (ja) * 1991-01-17 1992-08-31 Nec Corp プラスチックｐｇａパッケージ
JP2822996B2 (ja) * 1996-10-17 1998-11-11 日本電気株式会社 半導体装置
JPH10199930A (ja) * 1996-12-28 1998-07-31 Casio Comput Co Ltd 電子部品の接続構造および接続方法
JPH11297759A (ja) * 1998-04-08 1999-10-29 Seiko Epson Corp 半導体チップの実装構造および液晶表示装置
US6259608B1 (en) * 1999-04-05 2001-07-10 Delphi Technologies, Inc. Conductor pattern for surface mount devices and method therefor
JP2001319992A (ja) * 2000-02-28 2001-11-16 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2005183464A (ja) * 2003-12-16 2005-07-07 Nitto Denko Corp 配線回路基板

Also Published As

Publication number Publication date
CN100397624C (zh) 2008-06-25
JP2005183465A (ja) 2005-07-07
US7087844B2 (en) 2006-08-08
KR20050061342A (ko) 2005-06-22
US20050139371A1 (en) 2005-06-30
EP1545170B1 (de) 2010-08-25
JP4133786B2 (ja) 2008-08-13
TWI346378B (en) 2011-08-01
KR101088330B1 (ko) 2011-11-30
EP1545170A1 (de) 2005-06-22
TW200525710A (en) 2005-08-01
CN1630068A (zh) 2005-06-22

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