DE602004029193D1 - Pufferschaltung - Google Patents

Pufferschaltung

Info

Publication number
DE602004029193D1
DE602004029193D1 DE602004029193T DE602004029193T DE602004029193D1 DE 602004029193 D1 DE602004029193 D1 DE 602004029193D1 DE 602004029193 T DE602004029193 T DE 602004029193T DE 602004029193 T DE602004029193 T DE 602004029193T DE 602004029193 D1 DE602004029193 D1 DE 602004029193D1
Authority
DE
Germany
Prior art keywords
buffer circuit
buffer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004029193T
Other languages
English (en)
Inventor
Naoki Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE602004029193D1 publication Critical patent/DE602004029193D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
DE602004029193T 2003-12-09 2004-12-07 Pufferschaltung Active DE602004029193D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003410115 2003-12-09
PCT/JP2004/018214 WO2005057229A1 (ja) 2003-12-09 2004-12-07 バッファー回路及びドライバ回路

Publications (1)

Publication Number Publication Date
DE602004029193D1 true DE602004029193D1 (de) 2010-10-28

Family

ID=34674921

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004029193T Active DE602004029193D1 (de) 2003-12-09 2004-12-07 Pufferschaltung

Country Status (8)

Country Link
US (1) US7355432B2 (de)
EP (1) EP1703291B1 (de)
JP (1) JP4806567B2 (de)
KR (1) KR101071463B1 (de)
CN (1) CN1890573B (de)
DE (1) DE602004029193D1 (de)
TW (1) TWI359277B (de)
WO (1) WO2005057229A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7652466B2 (en) * 2007-07-29 2010-01-26 Advantest Corporation Buffer circuit, amplifier circuit, and test apparatus
US7962110B2 (en) * 2008-02-14 2011-06-14 Advantest Corporation Driver circuit and test apparatus
US8230281B2 (en) * 2009-04-13 2012-07-24 Altera Corporation Techniques for boundary scan testing using transmitters and receivers
KR101629793B1 (ko) 2014-03-17 2016-06-15 주식회사 앤코스메슈 모렐버섯의 생산을 위한 배지 조성물
US11283436B2 (en) 2019-04-25 2022-03-22 Teradyne, Inc. Parallel path delay line
US10942220B2 (en) * 2019-04-25 2021-03-09 Teradyne, Inc. Voltage driver with supply current stabilization
US11119155B2 (en) 2019-04-25 2021-09-14 Teradyne, Inc. Voltage driver circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601965B2 (ja) * 1977-12-02 1985-01-18 株式会社日立製作所 増幅回路
JPS5646310A (en) * 1979-09-21 1981-04-27 Pioneer Electronic Corp Amplifying circuit
US4791312A (en) * 1987-06-08 1988-12-13 Grumman Aerospace Corporation Programmable level shifting interface device
JP3235084B2 (ja) * 1990-06-18 2001-12-04 ハリス コーポレーシヨン 低いオフセットをもち、増幅率が１のバッファ・アンプ
DE4111999A1 (de) * 1991-04-12 1992-10-15 Hartmut Koellner Wandlerschaltung
US5365118A (en) * 1992-06-04 1994-11-15 Linear Technology Corp. Circuit for driving two power mosfets in a half-bridge configuration
JPH0738343A (ja) * 1993-07-19 1995-02-07 Columbia Techno:Kk 増幅器の保護回路
JP3490165B2 (ja) * 1994-12-15 2004-01-26 株式会社アドバンテスト ドライバ回路
US5654655A (en) 1994-05-27 1997-08-05 Advantest Corporation Driver circuit for semiconductor test system
JP3399742B2 (ja) * 1996-05-31 2003-04-21 株式会社日立製作所 入力バッファ回路
KR100433799B1 (ko) * 1998-12-03 2004-06-04 가부시키가이샤 히타치세이사쿠쇼 전압구동형 스위칭 소자의 게이트 구동회로
US6275023B1 (en) * 1999-02-03 2001-08-14 Hitachi Electronics Engineering Co., Ltd. Semiconductor device tester and method for testing semiconductor device
JP3929289B2 (ja) * 2001-11-12 2007-06-13 株式会社ルネサステクノロジ 半導体装置

Also Published As

Publication number Publication date
KR20060122895A (ko) 2006-11-30
CN1890573B (zh) 2010-06-16
EP1703291B1 (de) 2010-09-15
KR101071463B1 (ko) 2011-10-10
EP1703291A4 (de) 2009-07-01
TW200525158A (en) 2005-08-01
US20060273832A1 (en) 2006-12-07
TWI359277B (en) 2012-03-01
US7355432B2 (en) 2008-04-08
JP4806567B2 (ja) 2011-11-02
EP1703291A1 (de) 2006-09-20
CN1890573A (zh) 2007-01-03
WO2005057229A1 (ja) 2005-06-23
JPWO2005057229A1 (ja) 2007-07-05

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