DE60037599T2 - Herstellungsverfahren für halbleiteranordnung mit reduzierter signalwegverzögerungszeit - Google Patents

Herstellungsverfahren für halbleiteranordnung mit reduzierter signalwegverzögerungszeit Download PDF

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Publication number
DE60037599T2
DE60037599T2 DE60037599T DE60037599T DE60037599T2 DE 60037599 T2 DE60037599 T2 DE 60037599T2 DE 60037599 T DE60037599 T DE 60037599T DE 60037599 T DE60037599 T DE 60037599T DE 60037599 T2 DE60037599 T2 DE 60037599T2
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DE
Germany
Prior art keywords
layer
material layer
density
porous material
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60037599T
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German (de)
English (en)
Other versions
DE60037599D1 (de
Inventor
Manfred Horstmann
Karsten Wieczorek
Gert Burbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE60037599D1 publication Critical patent/DE60037599D1/de
Application granted granted Critical
Publication of DE60037599T2 publication Critical patent/DE60037599T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE60037599T 2000-01-05 2000-07-31 Herstellungsverfahren für halbleiteranordnung mit reduzierter signalwegverzögerungszeit Expired - Lifetime DE60037599T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US475572 1995-06-07
US09/475,572 US6541863B1 (en) 2000-01-05 2000-01-05 Semiconductor device having a reduced signal processing time and a method of fabricating the same
PCT/US2000/020886 WO2001050527A1 (en) 2000-01-05 2000-07-31 A semiconductor device having a reduced signal processing time and a method of fabricating the same

Publications (2)

Publication Number Publication Date
DE60037599D1 DE60037599D1 (de) 2008-02-07
DE60037599T2 true DE60037599T2 (de) 2008-04-30

Family

ID=23888165

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60037599T Expired - Lifetime DE60037599T2 (de) 2000-01-05 2000-07-31 Herstellungsverfahren für halbleiteranordnung mit reduzierter signalwegverzögerungszeit

Country Status (6)

Country Link
US (1) US6541863B1 (enExample)
EP (1) EP1245045B1 (enExample)
JP (1) JP2003519924A (enExample)
KR (1) KR100698495B1 (enExample)
DE (1) DE60037599T2 (enExample)
WO (1) WO2001050527A1 (enExample)

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KR100350111B1 (ko) * 2000-02-22 2002-08-23 삼성전자 주식회사 반도체 장치의 배선 및 이의 제조 방법
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6756620B2 (en) * 2001-06-29 2004-06-29 Intel Corporation Low-voltage and interface damage-free polymer memory device
US7294567B2 (en) * 2002-03-11 2007-11-13 Micron Technology, Inc. Semiconductor contact device and method
JP2004014815A (ja) * 2002-06-07 2004-01-15 Hitachi Ltd 半導体装置及びその製造方法
KR100416627B1 (ko) * 2002-06-18 2004-01-31 삼성전자주식회사 반도체 장치 및 그의 제조방법
US7382740B2 (en) * 2004-01-13 2008-06-03 Meshnetworks, Inc. System and method to perform smooth handoff of mobile terminals between fixed terminals in a network
US7709903B2 (en) * 2007-05-25 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Contact barrier structure and manufacturing methods
US7834456B2 (en) * 2009-01-20 2010-11-16 Raytheon Company Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate
US8633520B2 (en) 2010-10-21 2014-01-21 Samsung Electronics Co., Ltd. Semiconductor device
KR102733881B1 (ko) * 2016-09-12 2024-11-27 삼성전자주식회사 배선 구조체를 갖는 반도체 소자
KR102450580B1 (ko) * 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
JP7531981B2 (ja) * 2019-07-18 2024-08-13 東京エレクトロン株式会社 領域選択的堆積における横方向のフィルム成長を緩和するための方法

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US4380865A (en) * 1981-11-13 1983-04-26 Bell Telephone Laboratories, Incorporated Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
JPS63127551A (ja) * 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
JPH01235254A (ja) * 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
US6017811A (en) * 1993-09-09 2000-01-25 The United States Of America As Represented By The Secretary Of The Navy Method of making improved electrical contact to porous silicon
EP0733269B1 (en) * 1993-12-06 2002-01-16 QinetiQ Limited Porous semiconductor material
US5494858A (en) * 1994-06-07 1996-02-27 Texas Instruments Incorporated Method for forming porous composites as a low dielectric constant layer with varying porosity distribution electronics applications
US5504042A (en) 1994-06-23 1996-04-02 Texas Instruments Incorporated Porous dielectric material with improved pore surface properties for electronics applications
JPH08125016A (ja) * 1994-10-24 1996-05-17 Sony Corp 半導体装置の製造方法
KR0147939B1 (ko) 1994-11-11 1998-09-15 배순훈 투사형 화상표시장치의 화소보정장치
US5691238A (en) 1995-06-07 1997-11-25 Advanced Micro Devices, Inc. Subtractive dual damascene
US5821621A (en) * 1995-10-12 1998-10-13 Texas Instruments Incorporated Low capacitance interconnect structure for integrated circuits
JP3378135B2 (ja) * 1996-02-02 2003-02-17 三菱電機株式会社 半導体装置とその製造方法
WO1998000862A1 (en) 1996-06-28 1998-01-08 Advanced Micro Devices, Inc. Solid porous insulated conductive lines
US5744865A (en) * 1996-10-22 1998-04-28 Texas Instruments Incorporated Highly thermally conductive interconnect structure for intergrated circuits
JP3123449B2 (ja) * 1996-11-01 2001-01-09 ヤマハ株式会社 多層配線形成法
JP3984689B2 (ja) * 1996-11-11 2007-10-03 キヤノン株式会社 インクジェットヘッドの製造方法
US6008540A (en) * 1997-05-28 1999-12-28 Texas Instruments Incorporated Integrated circuit dielectric and method
US6407441B1 (en) * 1997-12-29 2002-06-18 Texas Instruments Incorporated Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications
JPH11312733A (ja) * 1998-04-28 1999-11-09 Nkk Corp 集積回路装置の製造方法
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US6376859B1 (en) * 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation
US6090724A (en) * 1998-12-15 2000-07-18 Lsi Logic Corporation Method for composing a thermally conductive thin film having a low dielectric property

Also Published As

Publication number Publication date
EP1245045B1 (en) 2007-12-26
KR20020065641A (ko) 2002-08-13
US6541863B1 (en) 2003-04-01
DE60037599D1 (de) 2008-02-07
JP2003519924A (ja) 2003-06-24
EP1245045A1 (en) 2002-10-02
KR100698495B1 (ko) 2007-03-23
WO2001050527A1 (en) 2001-07-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,