WO1998000862A1

WO1998000862A1 - Solid porous insulated conductive lines

Info

Publication number: WO1998000862A1
Application number: PCT/US1997/001713
Authority: WO
Inventors: Yowjuang W. Liu; Homi Fatemi; Nick Kepler; Matthew S. Buynoski; John T. Yue
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1996-06-28
Filing date: 1997-02-11
Publication date: 1998-01-08

Abstract

A method of forming low dielectric constant insulation (14) between those pairs of conductive lines (12), of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a fluid material containing insulating solids, such as a silicate, and drying said fluid material at a temperature and time so as to create, in the gap (31), a microporous material containing a gas with a dielectric constant of slightly above 1 or a large void whose dielectric constant is slightly greater than 1. Preferably the insulating solid is tetraethylorthosilicate. The resultant method forms an insulating material in the gaps of the conductive lines which has porosity in the range of about 0.6/um3 to about 2.0/um3 with a pore size in the range of 25 nm to 500 nm, and the density ranges from 0.01 to about 0.8 gram/cm3. The composite dielectric constant of the porous insulating material is in the range of about 1.1 to about 2.0.

Description

SOLID POROUS INSULATED CONDUCTIVE LIKES

FIELD OF THE INVENTION This invention relates to the fabrication of integrated circuit semiconductor devices and more particularly, to forming a low dielectric constant insulation between metal conductive lines which provide the interconnection between the active and/or passive elements of the integrated circuit, and further relates to the novel integrated circuit semiconductor device structures resulting therefrom.

BACKGROUND OF THE INVENTION In very large scale integrated (VLSI) circuit devices, several wiring layers are required to connect together the active and/or passive elements in a VLSI semiconductor chip. The interconnection structure consists of thin conductive lines separated by insulation in one layer or level and connected through vias or studs from contacts of the elements of the semiconductor chip or to a similar layer in another level of interconnections. This interconnection structure is similar to a transmission line in that there is a propagation delay of the signals being transmitted in these wiring layers. The delay is referred to as RC delay because it is a result of the resistance (R) of the material of the wire and the capacitance (C) between adjacent wires. With the trend of higher and higher levels of integration in semiconductor devices to ultra large scale integrated (ULSI) circuits, the space or gap between the wires or conductive lines to be filled with insulation is becoming extremely narrow between some of the conductive lines, such as those that are about 0.5 microns and smaller. Such a narrow space or gap between conductive lines increases the capacitance and places greater demands on the insulating properties of the insulation between such conductive lines. Capacitance (C) is the product of dielectric constant (DC) of the insulating material times the area (A) of the opposing faces of the conductive Hne divided by the distance (D) between the conductive lines. With a decrease in distance (D) , the capacitance (C) increases. Since signal delay of signal transmitted on the conductive line is controlled by the RC constant, an increase in capacitance (C) degrades the performance of the integrated circuit. At the present state of the art, the insulating material used to fill these gaps is a sil-icon containing compound, such as silicon dioxide, which has a dielectric constant (DC) of between 3.5 and 4.0. A vacuum has a perfect dielectric constant (DC) and is the basis for the measurement of the dielectric constant of other materials. For example, air and other insulating gases have a dielectric constant (DC) of slightly greater than 1, but less than 1.1. Air has a dielectric constant of 1.00059 and oxygen (0-) has a dielectric constant of

1.000523. The use of insulating material with dielectric constants (DC) lower than 3.5 in the narrow gap will lower the capacitance (C) and offset the increase caused by the smaller distance (D) between adjacent conductive lines. Attempts have been made to use organic insulating materials, such as polyimides which have a DC of between 3.2-3.4, but these materials are hygroscopic and any absorbed moisture can potentially cause corrosion of metal lines. Other possible insulating materials are boron nitride (BN_X) and fluorinated silicon oxide (SiO-F_y) , but they also have dielectric constants above 3.

In addition to the demands placed on the insulating property of the insulation between the conductive lines, these narrow gaps of about 0.5 microns and smaller make it much more difficult to deposit the insulating material into the gaps so that the gaps may not be completely and properly filled. In addition, when the height of the conductive line is increased, this increased height makes it still more difficult to fill, especially when the aspect ratio is 2 to l or greater with a gap distance of 0.5 microns or smaller. Aspect ratio is the height (h) of the conductive line divided by the distance (d) or gap between the conductive lines. It is pointed out in U.S. Patent No. 5,124,014 to Pang-Dow Foo et al. that when the gap or distance (d) is less than the (h) of the conductive line, it is difficult to fill uniformly. U.S. Patent No. 5,275,977 to Otsubo et al. confirms this problem and the inventors of both patents set the same objective for their processes; namely, the formation of the insulating film free of voids. Another concern in filling the conductive lines with insulation is the temperature necessary to deposit the insulating material. Above about 400°C, hillocks tend to form in the aluminum conductive lines and, if the growth is lateral, it can bridge the narrow gap and create a short in the conductive lines.

The disclosure in the Foo et al. patent describes a method for forming void free insulating layers between the conductive lines and it suggests that, from a detrimental standpoint, voids will form under certain conditions. However, this patent fails to recognize the advantage of voids surrounded by the insulating material in narrow gaps between conductive lines.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for filling the gaps between metal conductive lines with an insulating material such that at least the narrow gaps between the conductive lines have a significantly improved dielectric constant.

Another object of the present invention is to provide an alternative process for filling the narrow gaps between conductive lines with insulation with significantly improved dielectric constant that also provides a barrier to hillocks.

Still another object of the present invention is to provide a integrated circuit semiconductor device with a novel insulating structure between at least the narrow gaps having a significantly improved dielectric constant.

In accordance with the present invention, the method comprises: depositing a fluid insulating material containing solids or solid material having a dielectric constant of not greater than about 4.0 on a patterned surface of metal conductive lines with at least one pair of lines having a narrow gap between them, and drying the fluid material under such conditions that the solids form microgaps containing a gas with a dielectric constant of slightly above 1 throughout the areas between the conductive lines, whereby the dielectric constant of the composite insulation of solids and the gas is not greater than about 3.0. Preferably, the porosity of the dried insulating material is in the range of about 0.6/um³ to about 2.0 pores/um³ with a pore size in the range of 25 nm to 500 nm, and the density ranges from 0.01 to about 0.8 gram/cm³, and the dielectric constant of the composite insulation preferably ranges from about l.l to about 2.0. Although a number of different solid materials such as spin on glass and fluorinated spin on glass materials can be used to create a porous structure, preferably the solid material is a silicate and a particularly suitable silicate is tetraethylorthosilicate (TEOS) which has been treated with trimethylchlorosilane (TMCS) to increase its mechanical strength. In fluid form, the solid material is mixed in liquid which, herein, is ethanol and water at a temperature of 60 to 80°C when TEOS is the solid material. In accordance with another aspect of the present invention, an integrated circuit semiconductor device with interconnection levels having at least one narrow gap between a pair of conductive lines with such gap being filled with a porous insulating material having a dielectric constant of not greater than about 3 and with a porosity range of about 0.6 to about 2.0 pores/um³. It should be noted that the above described prior art patents fail to teach a method for filling narrow gaps between conductive lines with a porous insulating material. These patents further fail to recognize and even teach away from the performance advantage gained by using a porous or void containing insulating material in the narrow gaps to achieve a composite lower dielectric constant and, hence, reduced capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiments of the invention with reference in the drawings, in which: Figure l is a plan view of a portion of a VLSI integrated circuit metallization layer during fabrication of a semiconductor chip prior to being covered with a layer of insulating material.

Figure 2 is a cross-sectional view of the metallization layer taken- along 2-2 of Figure 1.

Figures 3, 4 and 5 are enlarged cross-sectional views of a section of Figure 2 as indicated by vertical lines 3-3 and 3a-3a showing early, intermediate and final stages of a prior art method for coating an insulating layer on the metallization layer. Figures 6, 7, 8, 9 and 10 are enlarged cross- sectional views of the same section of Figure 2 as in Figure 3 showing beginning, early, intermediate and final stages of the preferred method of the present invention for filling the gaps in the metallization layer with porous insulating material.

Figures 11, 12, 13, 14 and 15 are enlarged cross-sectional views of the same section of Figure 2 as in Figure 3 showing early, intermediate and final stages of an alternative method of the present invention for filling the gaps in the metallization layer with porous insulating material.

Figure 16 is a further enlarged cross-seconal views of only the narrow gap of Figure 2 showing one form of the porous structure of the present invention.

Figure 17 is a further enlarged cross-seconal views of only the narrow gap of Figure 2 showing another form of the porous structure of the present invention.

Figures IS and 19 are the porous structures of Figures 16 and 17 with a-partial layer of conventional insulating material underlying and a full layer of the insulating material on top of the porous structures.

Figure 20 is a partial cross-sectional view of an integrated circuit device with multilevel metallization showing the microporous insulation of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

Referring now to the drawings and, more particularly to Figures 1 and 2, a portion of a partially complete metallization layer 10 is shown disposed on an insulating layer 11 and with a plurality of conductive lines 12 having narrow gaps or openings 14a, intermediate gaps 14b and wide gaps 14c between the conductive lines.

A cross-section of this metallization layer 10 is shown in Figure 2 and it includes a conductive line 15 in the underlying metallization layer with vias 16a and 16b connecting that conductive line with two of the lines of the metallization layer 10. An insulating material must be deposited in the gaps or openings 14 as shown in Figures l and 2 to complete the metallization layer 10. Heretofore, this was accomplished by chemical vapor deposition (CVD) of precursors of the insulating material, such as silane (SiH and oxygen (0-) . Because of smaller gaps, such as 0.5 microns or less, between the conductive lines 12 and the possible formation of small voids in filling such narrow gaps, a present method uses the combination of simultaneously depositing and etching the insulating material to fill all of the gaps without any small voids. This method is shown in Figures 3, 4 and 5 at early, intermediate, and near final stages of filling the gaps 14a, 14b and 14c, respectively, between conductive lines 12 with a conformal insulating material 17, such as when the source of silicon is tetraethylorthosilicate (TEOS) or tetramethylcyclotetrasilane (TMCTS) to react with 0₂. Either a single chamber plasma reactor or a dual chamber, such as an Electron Cyclotron Resonance (ECR) reactor are used to simultaneously deposit Si0₂ and etch the deposited Si0₂ with either 0₂ or Argon (Ar) providing ions for sputter etching or an etching gas, such as carbon tetrafluoride (CF₄) for chemical etching. In the prior method using an ECR reactor, a conformal Si0₂ layer is deposited anisotropically or unidirectionally parallel to the sidewalls of the conductive lines 12 so as to minimize any buildup of the deposited Si0₂ on the shoulders 18 of the conductive lines as best shown in Figure 3. In addition, the deposited SiO- is etched at approximately a 45° angle during deposition, which causes the shoulders 18 to take on a sloped appearance as shown in Figures 3-5 and further reduces any possibility of deposited Si0₂ bridging over the gaps or openings 14a, 14b and 14c to create a void.- Thus, the combination of conformal source material for the insulating layer, unidirectional deposition, and sputter or chemical etching provides void free insulation between and on top of the conductive lines 12. The dielectric constant of the insulation between the conductive lines is the sole dielectric constant of the deposited insulating material and, since it is Si0₂, the dielectric constant of the prior art insulating material between the narrow gap 14a is in the range of 3.5 to 4.

In accordance with the present invention, it has been discovered that voids or pores within an insulating material are beneficial in filling a narrow gap or opening 14a because the voids or pores have a lower dielectric constant than any of the solid inorganic insulating materials, such as Si0₂, or even organic insulating materials, such as polyimide, and the combination of the solid insulating material and voids or pores of the proper size and quantity yields a dielectric constant of at least about 3 and lower. The voids or pores in a gap or opening of 0.5 microns or less with an aspect ratio of about 2 to l or greater relative to the conductive line's height provides a substantial improvement in the capacitance of the gap and thereby the RC delay of the conductive lines 12a and 12b on either side of the gap 14a. A method of the—present invention for achieving a porous insulating material containing voids or pores of the proper size is shown sequentially in Figures 6 , 7 , 8 , 9 and 10. The interconnection structure at the start of the method is the same as Figure 2 of the prior art. In Figure 6, which is an enlarged partial view of Figure 2, a deposited and planarized insulating layer 11 is partially shown with a layer on conductive lines 12 disposed thereon and with gaps or spaces 14a, 14b, and 14c between the conductive lines 12. To fill the gaps or spaces I4a-c between the conductive lines 12, a fluid material 20 of either a slurry, mixture, solution or vapor, depending on its composition, is deposited on the conductive lines 12. Herein the fluid material contains a silicate, which has a dielectric constant of about 3.9 and which is tetraethylorthosilicate (TEOS) combined with tri ethylchlorthosilicate (TMCS) to increase the mechanical strength of TEOS and is combined with a liquid. In the present instance, the liquid is ethanol and water in a preferred volume ratio of 1 to 1 with 80% by atomic weight of a silicate to form a fluid material having an absolute viscosity in the range of 3 to 5 centipoise at 20°C. Depending upon the dissolved or dispersed insulating material, the liquid, the ratio, if more than one liquid, and the atomic weight percentage of the insulating material to the liquid will change as will be understood by one skilled in the art to maintain the viscosity of the liquid composition within the range of 2 to 7 centipoise. The fluid material 20, preferably is spin coated on the conductive lines 12 of Figure 6 to fill the openings 14a, 14b, and 14c as shown in Figure 7a. The gaps or spaces 14a-c are over filled with the fluid material 20 as shown in Figure 7b, followed by heating to temperature and time sufficient to evaporate the liquid in the fluid material and preferably within a temperature range of 200°C to 300°C and for a time of ₁5 minutes to 30 minutes, thereby creating micropores or microvoids 21 as shown in Figure 8a-d. If in driving off the liquid in the fluid material 20, the dried insulating material may shrink and below the level of the top of the conductive lines 12 as shown in Figure 8a, additional fluid material 20a is deposited on the dried insulating material 21, herein again by spin coating the material, above the top of the conductive lines 12 as shown in Figure 8b. The additional fluid material 20a is dried by heating within the preferred temperature and time range and micropores or microvoids 2la are formed throughout the gaps or spaces 14a-c. With this deposition of the additional fluid material 20a, when necessary, the gaps or spaces I4a-c are completely filled with micropores or microvoids and the conductive lines 12 are capped with this insulating material 21a on top of the previously deposited and dried insulating material 21 as shown in Figure 8c. If, upon drying, the fluid material 20 does not shrink, the micropore or microvoid insulating material will only need a single deposition and the resulting material will be as shown in Figure 8d. As a final step, the insulating surface 22 of the dried deposited insulating material 21 is planarized back by a suitable technique such as chem/mech polishing, as shown in Figure 9 so as to be level with top of the conductive lines 12. In the present instant, the thickness of the dried deposited micropore or microvoid insulating layer 21 is about 0.8 to 1.2 , which is the height of the conductive lines. To complete this level of the multilevel interconnections, an insulating material 23, herein silicon dioxide is deposited, preferable by chemical vapor deposition (CND) using silane as the silicon source, to a thickness of 0.8 to 1.2μ, on the conductive lines now filled with the micropore or microvoid insulating material 21 as shown in Figure 10.

In accordance with another aspect of the present invention, a thin conformal insulating layer 29 is first deposited on conductive lines 12 separated by gaps or spaces 14a, 14b, and 14c, and carried on underlying insulating layer 11 as shown in Figure 11. As previously described in the Background of the Invention, high temperature processing, above about 400° C, in the fabrication of semiconductor devices causes hillocks or protrusions to grow out of aluminum when it is used as the material for the conductive lines. As a safeguard against hillocks in this aspect of the invention, the thin conformal insulating layer 29 of about 50θA thickness on the sidewalls is deposited on conductive lines 12. Herein, TEOS is used as the source of conformal Siθ₂ and is deposited by chemical vapor deposition as is well known in the art. A conformal material is used to assure that a thin uniform insulating layer of sufficient thickness, such as 50θA, coats the sidewalls 12a and 12b of the opposing conductive lines 12 on either side of the gaps I4a-c, especially the narrow gap 14a which, because of the small distance, is the most susceptible to hillocks shorting its adjacent conductive lines. Because the subsequent fluid material 30 in the formation of micropore or microvoid insulation may contain liquids to which the TEOS deposited oxide is - soluble, the thickness of the conformal insulating material may be deposited thicker than 50θA, such as about 70θA, in order to achieve a resultant thickness of 50θA. The remaining steps of this embodiment of the present invention for achieving a porous insulating material containing voids or pores of the proper size is shown sequentially in Figures 12a-b, 13a-d, 14 and 15. To fill the gaps or spaces 14a-c between the conductive lines 12, a fluid material 30 of either a slurry, mixture, solution or vapor, depending on its composition, is deposited on the conductive lines 12. Herein the fluid material again contains a silicate, which has a dielectric constant of about .9 and which is tetraethylorthosilicate (TEOS) combined with tri ethylchlorthosilicate (TMCS) to increase the mechanical strength of TEOS and is combined with a liquid. In the present instance, the liquid is ethanol and water in a preferred volume ratio of 1 to 1 with 80% by atomic weight of a silicate to form a fluid material having a viscosity in the range of 3 to 5 centipoise at 20°C. The fluid material 30, preferably is spin coated on the conductive lines 12 of Figure 11 to fill the openings 14a, 14b, and 14c as shown in Figure 12a. The gaps or spaces I4a-c are over filled with the fluid material 30 as shown in Figure 12b, followed by heating to temperature and time sufficient to evaporate the liquid in the fluid material and preferably within a temperature range of 200°C to 300°C and for a time of 15 minutes to 30 minutes, thereby creating micropores or microvoids 31 as shown in Figure I3a-d. If in driving off the liquid in the fluid material 30, the dried insulating material may shrink and below the level of the top of the conductive lines 12 as shown in Figure 13a, additional fluid material 30a is deposited on the dried insulating material 31, herein again by spin coating the material, above the top of the conductive lines 12 as shown in Figure 13b. The additional fluid material 30a is dried by heating within the preferred temperature and time range and micropores or microvoids 31a are formed throughout the gaps or spaces 1 a-c. With this deposition of the additional fluid material 30a, when necessary, the gaps or spaces I4a-c are completely filled with micropores or microvoids and the conductive lines 12 are capped with this insulating material 31a on top of the previously deposited and dried insulating material 31 as shown in Figure 13c. If, upon drying, the fluid material 30 does not shrink, the micropore or microvoid insulating material will only need a single deposition and the resulting material will be as shown in Figure 8d. As a final step, the insulating surface 32 of the dried deposited insulating material 31 is planarized back by a suitable technique such as chem/mech polishing, as shown in Figure 14 so as to be level with top of the conductive lines 12. In the present instant, the thickness of the dried deposited micropore or microvoid insulating layer 31 is about 0.8 to 1.2_/x, which is the height of the conductive lines. To complete the this level of the multilevel interconnections, an insulating material 33, herein silicon dioxide in deposited, preferable by chemical vapor deposition (CVD) using silane as the silicon source, to a thickness of 0.8 to 1.2_/--, on the conductive lines now filled with the micropore or microvoid insulating material 31 as shown in Figure 15.

As shown in Figures 16 and 17, the microporous insulation of the present invention can be in a variety of forms as long as microspaces or microgaps exist between the solid insulating material. In Figure 16, the icroporous insulation is in the form of microspheres 40 which encapsulate the low dielectric gas or air to yield a composite dielectric of less than about 3. In the embodiment of Figure 17, the microporous insulation comprises linear strands 41 of solid insulating material in random directions so that micropores or icrogaps are present between the strands. With both embodiments, the microspheres 40 and random strands 41 provide sufficient structure to support the deposition of a conventional insulating layer 11 as shown in Figures 18 and 19.

The method of the present invention yields a novel interconnection structure of an integrated circuit semiconductor device, which in accordance with another aspect of the present invention, comprises at least one interconnection level having at least one narrow gap between a pair of conductive lines with such gap being filled with a porous insulating material having a dielectric constant of not greater than about 3 and with a porosity range of about 0.6 to about 2.0 pores/um³. As partially shown in Figure 20, an integrated circuit device 50 comprises a silicon body 51 in which a plurality of active and passive devices, herein an exemplary Field Effect Transistor (FET) 52, is formed. The FET 52 includes a gate which preferably is a composite of polysilicon 54 on a gate insulator 55 and a metal silicate 56 on the polysilicon surface opposite the insulator 55 for electrical connection into the multilevel interconnections of the integrated circuit device. A source 57 and drain 58, each with Lightly Doped Drains (LDDs) , are disposed in the silicon body 51. Metal silicide layers 59a and 59b are formed on the surface of the source 57 and drain 48, which are insulated from the gate 53 by sidewalls of insulation on the sides of the gate, for electrical connection into the multilevel interconnections of the integrated circuit device. The FET 52 is isolated from other FETs or other active or passive devices by field oxidized areas 61. The devices, such as FET 52, both in and on the silicon body 50 are interconnected by multilevels of insulating layers 11 and conductive lines 12. As shown in Figure 20 vias 16 in contact with the source 57 and drain 48 connect to conductive lines 12 which are connected to other active and passive devices (not shown) and contact pads, such as 62, for input and output signals to and from the integrated circuit device 50. In accordance with the present invention and as shown in Figure 20, the gaps or spaces 14a, 14b, and 14c between the conductive lines 12 are filled with solid icroporous insulation so that the dielectric constant is not greater than about 3. Preferably, the insulating material is a silicate and the dielectric constant is in the range of about l.l to about

2.0. Although this invention has been described relative to specific insulating materials, conductive materials and apparatuses for depositing and etching these materials , it is not limited to the specific materials or apparatuses but only to their specific characteristics, such as being an insulating material with a dielectric constant of not greater than 4 and being capable of forming a porous structure when in the solid state. Other materials and apparatus can be substituted for those described herein which will be well understood by those skilled in the microelectronics arts after appreciating the present invention.

Claims

CLAIMS Having thus described the invention, what is claimed is:

1. A method of depositing an insulating material on a patterned surface of metal conductive lines separated by gaps on a substrate, with at least a pair of said conductive lines with opposing walls having a narrow gap of 0.5 microns or less between said walls, comprising the steps of: depositing fluid material containing insulating solids having a dielectric constant of not greater than 4.0 between the walls of the conductive lines; and drying the fluid material under such conditions of temperature and time that the solid insulating material forms, throughout the areas between the conductive lines, microspaces or micropores containing a gas with a dielectric constant—of slightly above l, whereby the dielectric constant of the composite insulation of solid material and the gas is not greater than about 3.0.

2. The method of Claim 1 wherein said dried insulating material has a porosity in the range of about

0.6/um³ to about 2.0/um³ with a pore size in the range of 25 nm to 500 nm, and the density ranges from 0.01 to about 0.8 gram/cm³.

3. The method of Claim 2 wherein said dried insulating material and the gas within the insulating material has a dielectric constant in the range of less than 2.0.

4. The method of Claim 1 wherein the deposited insulating solids are a silicon containing material.

5. The method of Claim 1 wherein, prior to depositing said fluid material containing insulating solids, a thin conformal insulating layer is deposited as a liner on the conductive lines.

6. The method of Claim 1 wherein the composite dielectric constant of the insulating liner, the insulating solids and the gas is not greater than about 3.0.

7. The method of Claim 4 wherein said silicon containing material is a silicate.

8. The method of Claim 7 wherein said silicate is tetraethylothosilicate.

9. The method of Claim 8 wherein said tetrathylothosilicate is combined with trimethylchlorthosilicate.

10. The method of Claim 5 wherein the dielectric constant is not greater than about 2.

11. An integrated circuit with semiconductor devices and multilevel interconnections with more than one level of conductive lines separated by solid insulating interlevel layers having interconnection therebetween for interconnecting the semiconductor devices and the inpu /output connections of the integrated circuit, comprising: at least one level of conductive lines having opposing walls separated by gaps and at least one of -said gaps being less than about 5μ ; and porous insulating material of sufficient structure to support a solid interlevel insulating layer and being disposed in gaps between opposing walls of said conductive lines and containing microspaces or micropores with the spaces or pores filled with a gas having a dielectric constant of slightly above 1 but less than 1.1, whereby the dielectric constant of the composite insulation of porous material and the gas is not greater than about 3.0.

12. The integrated circuit of Claim 11 wherein said porous insulating material has an porosity in the range of about 0.6/urn³ to about 2.0/um³ with a pore size in the range of 25 nm to 500 nm, and the density ranges from 0.01 to about 0.8 gram/cm³.

13. The integrated circuit of Claim 12 wherein said porous insulating material and the gas within the insulating material has a dielectric constant in the range of about 1.1 to about 2.0 or less.

14. The integrated circuit of Claim 11 wherein the porous insulating material is a silicon containing material.

15. The integrated circuit of Claim 12 wherein a thin conformal insulating layer is disposed on the walls on the conductive lines as an insulating liner.

16. The integrated circuit of Claim 15 wherein the composite dielectric constant of the insulating liner, the porous insulating material and the gas is not greater than about 3.0.

17. The integrated circuit of Claim 14 wherein said silicon containing material is a silicate.

18. The integrated circuit of Claim 17 wherein said silicate is tetraethylothosilicate.

19. The integrated circuit of Claim 18 wherein said tetrathylothosilicate is combined with trimethylchlorthosilicate.

20. The integrated circuit of Claim 19 wherein the dielectric constant is not greater than about 2.