DE4139200C2 - Verfahren zum Bilden einer inselförmigen isolierten Siliziumschicht in einer Halbleitervorrichtung - Google Patents

Verfahren zum Bilden einer inselförmigen isolierten Siliziumschicht in einer Halbleitervorrichtung

Info

Publication number
DE4139200C2
DE4139200C2 DE4139200A DE4139200A DE4139200C2 DE 4139200 C2 DE4139200 C2 DE 4139200C2 DE 4139200 A DE4139200 A DE 4139200A DE 4139200 A DE4139200 A DE 4139200A DE 4139200 C2 DE4139200 C2 DE 4139200C2
Authority
DE
Germany
Prior art keywords
layer
forming
oxide layer
semiconductor device
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE4139200A
Other languages
German (de)
English (en)
Other versions
DE4139200A1 (de
Inventor
Young Kwan Jun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of DE4139200A1 publication Critical patent/DE4139200A1/de
Application granted granted Critical
Publication of DE4139200C2 publication Critical patent/DE4139200C2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H10W10/17—
    • H10P95/06—
    • H10W10/0142—
    • H10W10/0145—
    • H10W10/0148—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Element Separation (AREA)
DE4139200A 1991-01-16 1991-11-28 Verfahren zum Bilden einer inselförmigen isolierten Siliziumschicht in einer Halbleitervorrichtung Expired - Lifetime DE4139200C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000640A KR940006696B1 (ko) 1991-01-16 1991-01-16 반도체 소자의 격리막 형성방법

Publications (2)

Publication Number Publication Date
DE4139200A1 DE4139200A1 (de) 1992-07-23
DE4139200C2 true DE4139200C2 (de) 1993-12-23

Family

ID=19309895

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4139200A Expired - Lifetime DE4139200C2 (de) 1991-01-16 1991-11-28 Verfahren zum Bilden einer inselförmigen isolierten Siliziumschicht in einer Halbleitervorrichtung

Country Status (5)

Country Link
US (1) US5229315A (enExample)
JP (1) JPH06105748B2 (enExample)
KR (1) KR940006696B1 (enExample)
DE (1) DE4139200C2 (enExample)
TW (1) TW218051B (enExample)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2608513B2 (ja) * 1991-10-02 1997-05-07 三星電子株式会社 半導体装置の製造方法
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
JP2914117B2 (ja) * 1993-08-28 1999-06-28 日本電気株式会社 半導体装置の製造方法
US5371036A (en) * 1994-05-11 1994-12-06 United Microelectronics Corporation Locos technology with narrow silicon trench
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
JP2000508474A (ja) * 1996-04-10 2000-07-04 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 改善された平坦化方法を伴う半導体トレンチアイソレーション
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5899727A (en) 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US6090685A (en) * 1997-08-22 2000-07-18 Micron Technology Inc. Method of forming a LOCOS trench isolation structure
KR100390894B1 (ko) * 1997-12-16 2003-10-10 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성방법
WO1999067817A1 (en) 1998-06-22 1999-12-29 Applied Materials, Inc. Silicon trench etching using silicon-containing precursors to reduce or avoid mask erosion
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
EP1077475A3 (en) * 1999-08-11 2003-04-02 Applied Materials, Inc. Method of micromachining a multi-part cavity
US6833079B1 (en) 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity
AU2003218144B2 (en) * 2002-03-13 2008-08-14 The Brigham And Women's Hospital, Inc. Method for overexpression of zwitterionic polysaccharides
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7560813B2 (en) * 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US7521806B2 (en) * 2005-06-14 2009-04-21 John Trezza Chip spanning connection
US7884483B2 (en) * 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7534722B2 (en) * 2005-06-14 2009-05-19 John Trezza Back-to-front via process
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US7358191B1 (en) * 2006-03-24 2008-04-15 Spansion Llc Method for decreasing sheet resistivity variations of an interconnect metal layer
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
KR101175393B1 (ko) * 2006-10-17 2012-08-20 쿠퍼 에셋 엘티디. 엘.엘.씨. 웨이퍼 비아 형성
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US7850060B2 (en) * 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US7748116B2 (en) * 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US7960210B2 (en) * 2007-04-23 2011-06-14 Cufer Asset Ltd. L.L.C. Ultra-thin chip packaging
EP2731617A4 (en) 2011-07-12 2015-07-01 Brigham & Womens Hospital LIPID-BASED PSA COMPOSITIONS, METHOD FOR THEIR INSULATION AND USE METHOD THEREFOR
CN108135167B (zh) 2015-08-19 2021-07-09 哈佛学院院长及董事 脂化psa组合物和方法
EP3484441A4 (en) 2016-07-15 2020-03-18 President and Fellows of Harvard College GLYCOLIPID COMPOSITIONS AND METHOD FOR USE

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621243A (ja) * 1985-06-27 1987-01-07 Toshiba Corp 半導体装置の製造方法
JPS6223128A (ja) * 1985-07-24 1987-01-31 Hitachi Ltd 素子分離領域の形成方法
JPH01286436A (ja) * 1988-05-13 1989-11-17 Fujitsu Ltd 半導体装置の製造方法
JPH02309652A (ja) * 1989-05-24 1990-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH0387045A (ja) * 1989-06-14 1991-04-11 Fujitsu Ltd 半導体装置及びその製造方法
JPH03109753A (ja) * 1989-09-25 1991-05-09 Fujitsu Ltd 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4704786A (en) * 1982-08-04 1987-11-10 Westinghouse Electric Corp. Method of forming a lateral bipolar transistor in a groove
JPS59124141A (ja) * 1982-12-28 1984-07-18 Toshiba Corp 半導体装置の製造方法
JPS61140175A (ja) * 1984-12-13 1986-06-27 Semiconductor Energy Lab Co Ltd 被膜作製方法
US4633290A (en) * 1984-12-28 1986-12-30 Gte Laboratories Incorporated Monolithic CMOS integrated circuit structure with isolation grooves
JPS61191043A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置
JPS6316751A (ja) * 1986-07-09 1988-01-23 Matsushita Electric Ind Co Ltd 転送電話装置
JP2576506B2 (ja) * 1987-05-27 1997-01-29 日本電気株式会社 Ｍｏｓ半導体装置
JPH0358484A (ja) * 1989-07-27 1991-03-13 Toshiba Corp 半導体装置とその製造方法
US5061652A (en) * 1990-01-23 1991-10-29 International Business Machines Corporation Method of manufacturing a semiconductor device structure employing a multi-level epitaxial structure
US9284888B2 (en) 2012-04-25 2016-03-15 General Electric Company System for supplying fuel to late-lean fuel injectors of a combustor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621243A (ja) * 1985-06-27 1987-01-07 Toshiba Corp 半導体装置の製造方法
JPS6223128A (ja) * 1985-07-24 1987-01-31 Hitachi Ltd 素子分離領域の形成方法
JPH01286436A (ja) * 1988-05-13 1989-11-17 Fujitsu Ltd 半導体装置の製造方法
JPH02309652A (ja) * 1989-05-24 1990-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH0387045A (ja) * 1989-06-14 1991-04-11 Fujitsu Ltd 半導体装置及びその製造方法
JPH03109753A (ja) * 1989-09-25 1991-05-09 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
KR920015603A (ko) 1992-08-27
US5229315A (en) 1993-07-20
JPH0555364A (ja) 1993-03-05
KR940006696B1 (ko) 1994-07-25
TW218051B (enExample) 1993-12-21
JPH06105748B2 (ja) 1994-12-21
DE4139200A1 (de) 1992-07-23

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
R071 Expiry of right
R071 Expiry of right