DE4127549C2 - - Google Patents

Info

Publication number
DE4127549C2
DE4127549C2 DE4127549A DE4127549A DE4127549C2 DE 4127549 C2 DE4127549 C2 DE 4127549C2 DE 4127549 A DE4127549 A DE 4127549A DE 4127549 A DE4127549 A DE 4127549A DE 4127549 C2 DE4127549 C2 DE 4127549C2
Authority
DE
Germany
Prior art keywords
reference potential
memory cell
memory
line
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4127549A
Other languages
German (de)
English (en)
Other versions
DE4127549A1 (de
Inventor
Shinichi Uramoto
Tetsuya Matsumura
Masahiko Yoshimoto
Kazuya Ishihara
Hiroshi Itami Hyogo Jp Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP40008190A external-priority patent/JP2611873B2/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE4127549A1 publication Critical patent/DE4127549A1/de
Application granted granted Critical
Publication of DE4127549C2 publication Critical patent/DE4127549C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5617—Multilevel ROM cell programmed by source, drain or gate contacting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE4127549A 1990-08-28 1991-08-20 Festwertspeicher zum speichern von mehrfachdaten Granted DE4127549A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP22706090 1990-08-28
JP40008190A JP2611873B2 (ja) 1990-12-01 1990-12-01 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE4127549A1 DE4127549A1 (de) 1992-03-05
DE4127549C2 true DE4127549C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-03-25

Family

ID=26527483

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4127549A Granted DE4127549A1 (de) 1990-08-28 1991-08-20 Festwertspeicher zum speichern von mehrfachdaten

Country Status (2)

Country Link
US (2) US5289406A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE4127549A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (74)

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US5497354A (en) * 1994-06-02 1996-03-05 Intel Corporation Bit map addressing schemes for flash memory
EP0763242B1 (en) * 1994-06-02 2001-07-11 Intel Corporation Sensing schemes for flash memory with multilevel cells
US5528534A (en) * 1995-03-21 1996-06-18 At&T Corp. High-density read-only memory employing multiple bit-line interconnection
JP3321516B2 (ja) * 1996-02-27 2002-09-03 シャープ株式会社 読み出し専用半導体記憶装置
US5790452A (en) * 1996-05-02 1998-08-04 Integrated Device Technology, Inc. Memory cell having asymmetrical source/drain pass transistors and method for operating same
US5926035A (en) * 1996-06-26 1999-07-20 Cypress Semiconductor Corp. Method and apparatus to generate mask programmable device
US5943488A (en) * 1996-06-26 1999-08-24 Cypress Semiconductor Corp. Method and apparatus to generate mask programmable device
US5949711A (en) * 1996-09-26 1999-09-07 Waferscale Integration, Inc. Dual bit memory cell
IL125604A (en) * 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6633496B2 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Symmetric architecture for memory cells having widely spread metal bit lines
US6430077B1 (en) 1997-12-12 2002-08-06 Saifun Semiconductors Ltd. Method for regulating read voltage level at the drain of a cell in a symmetric array
US6633499B1 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Method for reducing voltage drops in symmetric array architectures
US6348711B1 (en) 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
KR100299872B1 (ko) * 1998-06-29 2001-10-27 박종섭 다비트데이터기록제어회로
US6147893A (en) * 1999-01-27 2000-11-14 Vlsi Technology, Inc. Programmable read only memory with high speed differential sensing at low operating voltage
JP3206591B2 (ja) * 1999-02-08 2001-09-10 日本電気株式会社 多値マスクｒｏｍおよび多値マスクｒｏｍの読み出し方法
FR2794895B1 (fr) * 1999-06-11 2001-09-14 St Microelectronics Sa Dispositif semiconducteur integre de memoire morte
US6429063B1 (en) 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
US6490204B2 (en) 2000-05-04 2002-12-03 Saifun Semiconductors Ltd. Programming and erasing methods for a reference cell of an NROM array
US6928001B2 (en) 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US6396741B1 (en) 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6614692B2 (en) * 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6677805B2 (en) 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
US6643181B2 (en) 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US7098107B2 (en) 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6583007B1 (en) 2001-12-20 2003-06-24 Saifun Semiconductors Ltd. Reducing secondary injection effects
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
TWI258146B (en) * 2001-12-28 2006-07-11 Realtek Semiconductor Corp Curve lookup table method reducing memory space and data storage method
US6700818B2 (en) * 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
KR100470971B1 (ko) * 2002-08-01 2005-03-10 삼성전자주식회사 리드 전용 메모리 셀, 이 셀의 프로그램 방법, 이 셀의레이아웃 방법, 및 이 셀을 구비한 리드 전용 메모리 장치
US6826107B2 (en) * 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) * 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) * 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) * 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7050319B2 (en) * 2003-12-03 2006-05-23 Micron Technology, Inc. Memory architecture and method of manufacture and operation thereof
KR100521386B1 (ko) * 2004-01-12 2005-10-12 삼성전자주식회사 리드 온리 메모리에서의 커플링 현상을 방지하기 위한비트 셀 어레이
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060068551A1 (en) * 2004-09-27 2006-03-30 Saifun Semiconductors, Ltd. Method for embedding NROM
US7638850B2 (en) * 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US20060146624A1 (en) * 2004-12-02 2006-07-06 Saifun Semiconductors, Ltd. Current folding sense amplifier
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1686592A3 (en) * 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US20070141788A1 (en) * 2005-05-25 2007-06-21 Ilan Bloom Method for embedding non-volatile memory with logic circuitry
JP2007027760A (ja) * 2005-07-18 2007-02-01 Saifun Semiconductors Ltd 高密度不揮発性メモリアレイ及び製造方法
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US20070096199A1 (en) * 2005-09-08 2007-05-03 Eli Lusky Method of manufacturing symmetric arrays
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US20070087503A1 (en) * 2005-10-17 2007-04-19 Saifun Semiconductors, Ltd. Improving NROM device characteristics using adjusted gate work function
US20070120180A1 (en) * 2005-11-25 2007-05-31 Boaz Eitan Transition areas for dense memory arrays
US7352627B2 (en) * 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) * 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US20070173017A1 (en) * 2006-01-20 2007-07-26 Saifun Semiconductors, Ltd. Advanced non-volatile memory array and method of fabrication thereof
US8253452B2 (en) * 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7760554B2 (en) * 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7692961B2 (en) * 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US20070255889A1 (en) * 2006-03-22 2007-11-01 Yoav Yogev Non-volatile memory device and method of operating the device
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US20080008019A1 (en) * 2006-07-06 2008-01-10 Texas Instruments Incorporated High Speed Read-Only Memory
US7605579B2 (en) * 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US20080239599A1 (en) * 2007-04-01 2008-10-02 Yehuda Yizraeli Clamping Voltage Events Such As ESD
US7590001B2 (en) 2007-12-18 2009-09-15 Saifun Semiconductors Ltd. Flash memory with optimized write sector spares
US8861649B2 (en) * 2009-02-23 2014-10-14 Empire Technology Development Llc Power reduction in physical layer wireless communications
US9202588B1 (en) * 2014-09-23 2015-12-01 Nxp B.V. 1T compact ROM cell with dual bit storage for high speed and low voltage
US10453544B2 (en) * 2014-12-10 2019-10-22 Nxp Usa, Inc. Memory array with read only cells having multiple states and method of programming thereof
US9799409B2 (en) * 2016-03-25 2017-10-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Read-only memory (ROM) architecture with selective encoding

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608558B2 (ja) * 1977-03-23 1985-03-04 日本電気株式会社 読出し専用記憶装置
US4203159A (en) * 1978-10-05 1980-05-13 Wanlass Frank M Pseudostatic electronic memory
JPS5843838B2 (ja) * 1979-02-28 1983-09-29 富士通株式会社 読取り専用メモリ
US4327424A (en) * 1980-07-17 1982-04-27 International Business Machines Corporation Read-only storage using enhancement-mode, depletion-mode or omitted gate field-effect transistors
JPS61289598A (ja) * 1985-06-17 1986-12-19 Toshiba Corp 読出専用半導体記憶装置
JPS6325894A (ja) * 1986-07-18 1988-02-03 Hitachi Ltd 半導体記憶装置
JPS6342100A (ja) * 1986-08-08 1988-02-23 Fujitsu Ltd ３値レベルｒｏｍ
US4899308A (en) * 1986-12-11 1990-02-06 Fairchild Semiconductor Corporation High density ROM in a CMOS gate array

Also Published As

Publication number Publication date
US5289406A (en) 1994-02-22
DE4127549A1 (de) 1992-03-05
US5394355A (en) 1995-02-28

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: PRUFER & PARTNER GBR, 81545 MUENCHEN

8339 Ceased/non-payment of the annual fee