DE69621280T2 - Speichergerätschaltkreis und Verfahren zur gleichzeitigen Adressierung der Spalten einer Vielzahl von Banken einer Vielzahlbankspeicheranordnung - Google Patents

Speichergerätschaltkreis und Verfahren zur gleichzeitigen Adressierung der Spalten einer Vielzahl von Banken einer Vielzahlbankspeicheranordnung

Info

Publication number
DE69621280T2
DE69621280T2 DE69621280T DE69621280T DE69621280T2 DE 69621280 T2 DE69621280 T2 DE 69621280T2 DE 69621280 T DE69621280 T DE 69621280T DE 69621280 T DE69621280 T DE 69621280T DE 69621280 T2 DE69621280 T2 DE 69621280T2
Authority
DE
Germany
Prior art keywords
banks
columns
device circuitry
memory device
simultaneously addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69621280T
Other languages
English (en)
Other versions
DE69621280D1 (de
Inventor
Michael C Parris
H Kent Stalnaker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Promos Technologies Inc
Original Assignee
Mosel Vitelic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosel Vitelic Inc filed Critical Mosel Vitelic Inc
Publication of DE69621280D1 publication Critical patent/DE69621280D1/de
Application granted granted Critical
Publication of DE69621280T2 publication Critical patent/DE69621280T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69621280T 1995-04-11 1996-01-04 Speichergerätschaltkreis und Verfahren zur gleichzeitigen Adressierung der Spalten einer Vielzahl von Banken einer Vielzahlbankspeicheranordnung Expired - Fee Related DE69621280T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/419,909 US5671392A (en) 1995-04-11 1995-04-11 Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array

Publications (2)

Publication Number Publication Date
DE69621280D1 DE69621280D1 (de) 2002-06-27
DE69621280T2 true DE69621280T2 (de) 2002-10-02

Family

ID=23664256

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69621280T Expired - Fee Related DE69621280T2 (de) 1995-04-11 1996-01-04 Speichergerätschaltkreis und Verfahren zur gleichzeitigen Adressierung der Spalten einer Vielzahl von Banken einer Vielzahlbankspeicheranordnung

Country Status (5)

Country Link
US (1) US5671392A (de)
EP (1) EP0737981B1 (de)
JP (1) JPH09147551A (de)
KR (1) KR100386442B1 (de)
DE (1) DE69621280T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004060644B4 (de) * 2003-12-16 2014-02-06 Qimonda Ag Direktzugriffsspeicher, Speichersteuerung und Verfahren unter Verwendung von Vorladezeitgebern in einem Testmodus

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US6330644B1 (en) * 1994-10-27 2001-12-11 Canon Kabushiki Kaisha Signal processor with a plurality of kinds of processors and a shared memory accessed through a versatile control means
US5996106A (en) 1997-02-04 1999-11-30 Micron Technology, Inc. Multi bank test mode for memory devices
JPH10275460A (ja) * 1997-04-01 1998-10-13 Sega Enterp Ltd メモリ装置及びこれを用いた画像処理装置
US5996051A (en) * 1997-04-14 1999-11-30 Advanced Micro Devices, Inc. Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array
US5913928A (en) 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
US5959911A (en) * 1997-09-29 1999-09-28 Siemens Aktiengesellschaft Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices
GB2381103B (en) 1997-12-17 2003-06-04 Fujitsu Ltd Memory access methods and devices for use with random access memories
JPH11283395A (ja) * 1998-03-30 1999-10-15 Toshiba Microelectronics Corp 半導体記憶装置
US6088293A (en) * 1998-09-08 2000-07-11 Texas Instruments Incorporated Low-power column decode circuit
KR100517544B1 (ko) * 1999-01-20 2005-09-28 삼성전자주식회사 멀티-뱅크 플래시 메모리 장치
KR100331284B1 (ko) * 1999-12-29 2002-04-06 박종섭 병렬테스트회로를 갖는 메모리장치
US7302621B2 (en) * 2000-01-03 2007-11-27 Icoding Technology, Inc. High spread highly randomized generatable interleavers
US6775800B2 (en) * 2000-01-03 2004-08-10 Icoding Technology, Inc. System and method for high speed processing of turbo codes
US6320803B1 (en) * 2000-03-23 2001-11-20 Infineon Technologies Ac Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits
US6965527B2 (en) * 2002-11-27 2005-11-15 Matrix Semiconductor, Inc Multibank memory on a die
KR100558552B1 (ko) 2003-12-30 2006-03-10 삼성전자주식회사 반도체 메모리장치의 데이터 억세스회로
KR100576454B1 (ko) * 2004-03-22 2006-05-08 주식회사 하이닉스반도체 뱅크 선택이 가능한 병렬 테스트 회로 및 그 병렬 테스트방법
KR100618696B1 (ko) * 2004-04-28 2006-09-08 주식회사 하이닉스반도체 인식 정보를 갖는 메모리 장치
KR100781973B1 (ko) * 2006-05-08 2007-12-06 삼성전자주식회사 반도체 메모리 장치 및 그의 테스트 방법
JP2008065862A (ja) * 2006-09-04 2008-03-21 System Fabrication Technologies Inc 半導体記憶装置
US7631233B2 (en) * 2007-10-07 2009-12-08 United Memories, Inc. Data inversion register technique for integrated circuit memory testing
US7944773B2 (en) * 2008-04-30 2011-05-17 Micron Technology, Inc. Synchronous command-based write recovery time auto-precharge control
US8171234B2 (en) 2009-03-16 2012-05-01 Mosys, Inc. Multi-bank multi-port architecture
US20110228620A1 (en) * 2010-03-22 2011-09-22 Elite Semiconductor Memory Technology Inc. Testing method for semiconductor memory device
JP5954498B2 (ja) * 2013-07-29 2016-07-20 富士通株式会社 半導体記憶装置、及び、半導体記憶装置の試験方法
WO2016125202A1 (en) 2015-02-04 2016-08-11 Renesas Electronics Corporation Data transfer apparatus
WO2018044391A1 (en) 2016-09-02 2018-03-08 Rambus Inc. Memory component with input/output data rate alignment
US11449250B2 (en) 2019-10-14 2022-09-20 Micron Technology, Inc. Managing a mode to access a memory component or a logic component for machine learning computation in a memory sub-system

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
JPS60115099A (ja) * 1983-11-25 1985-06-21 Fujitsu Ltd 半導体記憶装置
US4598388A (en) * 1985-01-22 1986-07-01 Texas Instruments Incorporated Semiconductor memory with redundant column circuitry
JPS6212991A (ja) * 1985-07-10 1987-01-21 Fujitsu Ltd 半導体記憶装置
JP3532932B2 (ja) * 1991-05-20 2004-05-31 モトローラ・インコーポレイテッド 時間重複メモリ・アクセスを有するランダムにアクセス可能なメモリ
JPH0792790B2 (ja) * 1992-11-18 1995-10-09 野木 達夫 ベクトル並列計算機
US5386385A (en) * 1994-01-31 1995-01-31 Texas Instruments Inc. Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004060644B4 (de) * 2003-12-16 2014-02-06 Qimonda Ag Direktzugriffsspeicher, Speichersteuerung und Verfahren unter Verwendung von Vorladezeitgebern in einem Testmodus

Also Published As

Publication number Publication date
US5671392A (en) 1997-09-23
KR100386442B1 (ko) 2003-08-14
DE69621280D1 (de) 2002-06-27
EP0737981A2 (de) 1996-10-16
JPH09147551A (ja) 1997-06-06
EP0737981B1 (de) 2002-05-22
EP0737981A3 (de) 1997-07-30
KR960038618A (ko) 1996-11-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PROMOS TECHNOLOGIES, INC., HSINCHU, TW

8339 Ceased/non-payment of the annual fee