DE69718846D1 - Verfahren zum Speicherzugriff - Google Patents

Verfahren zum Speicherzugriff

Info

Publication number
DE69718846D1
DE69718846D1 DE69718846T DE69718846T DE69718846D1 DE 69718846 D1 DE69718846 D1 DE 69718846D1 DE 69718846 T DE69718846 T DE 69718846T DE 69718846 T DE69718846 T DE 69718846T DE 69718846 D1 DE69718846 D1 DE 69718846D1
Authority
DE
Germany
Prior art keywords
memory access
access method
memory
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69718846T
Other languages
English (en)
Other versions
DE69718846T2 (de
Inventor
Mcintyre, Jr
Anthony M Reipold
Daniel W Pechonis
Steven P Lindquist
Colleen M Collins
Robert L Winter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/660,702 external-priority patent/US6006288A/en
Priority claimed from US08/660,620 external-priority patent/US5875482A/en
Priority claimed from US08/660,028 external-priority patent/US5813041A/en
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69718846D1 publication Critical patent/DE69718846D1/de
Application granted granted Critical
Publication of DE69718846T2 publication Critical patent/DE69718846T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE69718846T 1996-06-06 1997-05-28 Verfahren zum Speicherzugriff Expired - Fee Related DE69718846T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/660,702 US6006288A (en) 1996-06-06 1996-06-06 Method and apparatus for adaptable burst chip select in a data processing system
US08/660,620 US5875482A (en) 1996-06-06 1996-06-06 Method and apparatus for programmable chip select negation in a data processing system
US08/660,028 US5813041A (en) 1996-06-06 1996-06-06 Method for accessing memory by activating a programmable chip select signal

Publications (2)

Publication Number Publication Date
DE69718846D1 true DE69718846D1 (de) 2003-03-13
DE69718846T2 DE69718846T2 (de) 2003-06-18

Family

ID=27418025

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69718846T Expired - Fee Related DE69718846T2 (de) 1996-06-06 1997-05-28 Verfahren zum Speicherzugriff

Country Status (5)

Country Link
EP (2) EP0811921B1 (de)
JP (1) JPH1083343A (de)
KR (1) KR100457478B1 (de)
DE (1) DE69718846T2 (de)
TW (1) TW363153B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6120621A (en) * 1996-07-08 2000-09-19 Alcan International Limited Cast aluminum alloy for can stock and process for producing the alloy
JP2002288036A (ja) * 2001-03-27 2002-10-04 Nec Corp メモリ読出し回路およびｉｃｅ
US6701422B2 (en) * 2001-03-29 2004-03-02 Koninklijke Philips Electronics N.V. Memory control system with incrementer for generating speculative addresses
DE10361059A1 (de) * 2003-12-22 2005-07-28 Micronas Gmbh Verfahren und Vorrichtung zum Steuern eines Speicherzugriffs
US7725665B2 (en) * 2004-06-30 2010-05-25 Renesas Technology Corp. Data processor
CN101689144B (zh) * 2007-06-19 2013-07-24 富士通株式会社 信息处理装置及其控制方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0731627B2 (ja) * 1985-08-10 1995-04-10 株式会社リコー メモリ−装置
JPH0644393B2 (ja) * 1986-04-08 1994-06-08 日本電気株式会社 半導体メモリ
IT1216087B (it) * 1988-03-15 1990-02-22 Honeywell Bull Spa Sistema di memoria con selezione predittiva di modulo.
EP0501621A3 (en) * 1991-02-26 1994-07-06 Hewlett Packard Co Address prediction and verification for burst cycle data reads
ATE185631T1 (de) * 1991-08-16 1999-10-15 Cypress Semiconductor Corp Dynamisches hochleistungsspeichersystem
JPH05108471A (ja) * 1991-10-17 1993-04-30 Matsushita Electric Ind Co Ltd メモリ装置
JP3639927B2 (ja) * 1993-10-04 2005-04-20 株式会社ルネサステクノロジ データ処理装置
JPH07129458A (ja) * 1993-10-29 1995-05-19 Kyocera Corp メモリ制御装置
US5502835A (en) * 1994-08-31 1996-03-26 Motorola, Inc. Method for synchronously accessing memory
US5651138A (en) * 1994-08-31 1997-07-22 Motorola, Inc. Data processor with controlled burst memory accesses and method therefor
JP3161254B2 (ja) * 1994-11-25 2001-04-25 株式会社日立製作所 同期式メモリ装置
KR0143317B1 (ko) * 1995-04-26 1998-08-17 김광호 양방향 액세스 가능한 대용량 메모리 장치

Also Published As

Publication number Publication date
EP0811921A2 (de) 1997-12-10
EP1197867A2 (de) 2002-04-17
KR980004047A (ko) 1998-03-30
EP1197867A3 (de) 2005-12-14
EP0811921A3 (de) 1998-09-23
TW363153B (en) 1999-07-01
DE69718846T2 (de) 2003-06-18
EP0811921B1 (de) 2003-02-05
KR100457478B1 (ko) 2005-04-06
JPH1083343A (ja) 1998-03-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee