DE3872737T2 - Verfahren zur kombinierung von "gate array"-schaltungen mit standardschaltungen auf ein gemeinsames halbleiterplaettchen. - Google Patents

Verfahren zur kombinierung von "gate array"-schaltungen mit standardschaltungen auf ein gemeinsames halbleiterplaettchen.

Info

Publication number
DE3872737T2
DE3872737T2 DE8888100942T DE3872737T DE3872737T2 DE 3872737 T2 DE3872737 T2 DE 3872737T2 DE 8888100942 T DE8888100942 T DE 8888100942T DE 3872737 T DE3872737 T DE 3872737T DE 3872737 T2 DE3872737 T2 DE 3872737T2
Authority
DE
Germany
Prior art keywords
circuits
combining
gate array
common semiconductor
semiconductor board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888100942T
Other languages
English (en)
Other versions
DE3872737D1 (de
Inventor
Elliot L Gould
Douglas W Kemerer
Ronald A Piro
Guy R Richardson
Deborah A Wellburn
Lance A Mcallister
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3872737D1 publication Critical patent/DE3872737D1/de
Application granted granted Critical
Publication of DE3872737T2 publication Critical patent/DE3872737T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/909—Macrocell arrays, e.g. gate arrays with variable size or configuration of cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8888100942T 1987-02-24 1988-01-22 Verfahren zur kombinierung von "gate array"-schaltungen mit standardschaltungen auf ein gemeinsames halbleiterplaettchen. Expired - Fee Related DE3872737T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/018,239 US4786613A (en) 1987-02-24 1987-02-24 Method of combining gate array and standard cell circuits on a common semiconductor chip

Publications (2)

Publication Number Publication Date
DE3872737D1 DE3872737D1 (de) 1992-08-20
DE3872737T2 true DE3872737T2 (de) 1993-03-04

Family

ID=21786931

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888100942T Expired - Fee Related DE3872737T2 (de) 1987-02-24 1988-01-22 Verfahren zur kombinierung von "gate array"-schaltungen mit standardschaltungen auf ein gemeinsames halbleiterplaettchen.

Country Status (7)

Country Link
US (1) US4786613A (de)
EP (1) EP0283655B1 (de)
JP (2) JPH0821701B2 (de)
BR (1) BR8800754A (de)
CA (1) CA1290076C (de)
DE (1) DE3872737T2 (de)
ES (1) ES2033346T3 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
US4831725A (en) * 1988-06-10 1989-05-23 International Business Machines Corporation Global wiring by removal of redundant paths
JPH02278848A (ja) * 1989-04-20 1990-11-15 Nec Corp 集積回路装置
US5015600A (en) * 1990-01-25 1991-05-14 Northern Telecom Limited Method for making integrated circuits
JP3027990B2 (ja) * 1991-03-18 2000-04-04 富士通株式会社 半導体装置の製造方法
WO1993012540A1 (en) * 1991-12-10 1993-06-24 Vlsi Technology, Inc. Integrated circuit with variable pad pitch
JPH08316331A (ja) * 1995-03-15 1996-11-29 Toshiba Corp 半導体集積回路及びその設計方法
FR2741475B1 (fr) * 1995-11-17 2000-05-12 Commissariat Energie Atomique Procede de fabrication d'un dispositif de micro-electronique comportant sur un substrat une pluralite d'elements interconnectes
TW392307B (en) * 1998-01-13 2000-06-01 Mitsubishi Electric Corp A method of the manufacture and the setup of the semiconductor apparatus
US6532581B1 (en) 1998-07-03 2003-03-11 Matsushita Electric Industrial Co., Ltd. Method for designing layout of semiconductor device, storage medium having stored thereon program for executing the layout designing method, and semiconductor device
TW519748B (en) * 2001-12-26 2003-02-01 Faraday Tech Corp Semiconductor device with substrate-triggered ESD protection
JP2004007472A (ja) * 2002-03-22 2004-01-08 Toshiba Corp 半導体集積回路、データ転送システム、及びデータ転送方法
JP2004221231A (ja) * 2003-01-14 2004-08-05 Nec Electronics Corp レイアウトパターン生成のための装置と方法、及びそれを用いた半導体装置の製造方法
US7095063B2 (en) * 2003-05-07 2006-08-22 International Business Machines Corporation Multiple supply gate array backfill structure
DE102004038063A1 (de) * 2004-07-30 2006-03-23 Infineon Technologies Ag Verfahren zur Herstellung einer Standardzellenanordnung und eine Vorrichtung zur Durchführung des Verfahrens
JP2012064854A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 半導体装置
US20210200927A1 (en) * 2019-12-31 2021-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Transistor Placement in Standard Cell Layout
US11663391B2 (en) 2021-08-25 2023-05-30 International Business Machines Corporation Latch-up avoidance for sea-of-gates

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US814122A (en) * 1904-06-25 1906-03-06 Henry G Eckstein Apparatus for the manufacture of moisture-proof cartons.
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS5890758A (ja) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp 相補形集積回路装置
FR2524206B1 (fr) * 1982-03-26 1985-12-13 Thomson Csf Mat Tel Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit
US4513307A (en) * 1982-05-05 1985-04-23 Rockwell International Corporation CMOS/SOS transistor gate array apparatus
JPS5943548A (ja) * 1982-09-06 1984-03-10 Hitachi Ltd 半導体集積回路装置
JPS60110137A (ja) * 1983-11-18 1985-06-15 Sanyo Electric Co Ltd 半導体装置
JPS60177650A (ja) * 1984-02-23 1985-09-11 Toshiba Corp 半導体装置およびその製造方法
US4570176A (en) * 1984-04-16 1986-02-11 At&T Bell Laboratories CMOS Cell array with transistor isolation
JPS60234231A (ja) * 1984-05-04 1985-11-20 Fuji Photo Film Co Ltd 磁気記録媒体
JPS60234341A (ja) * 1984-05-07 1985-11-21 Hitachi Ltd 半導体集回路装置
JPS6124250A (ja) * 1984-07-13 1986-02-01 Nippon Gakki Seizo Kk 半導体集積回路装置
JPS61123153A (ja) * 1984-11-20 1986-06-11 Fujitsu Ltd ゲ−トアレイｌｓｉ装置
JPS61202450A (ja) * 1985-03-05 1986-09-08 Nec Corp 半導体集積回路装置
JPH0785490B2 (ja) * 1986-01-22 1995-09-13 日本電気株式会社 集積回路装置

Also Published As

Publication number Publication date
US4786613A (en) 1988-11-22
EP0283655B1 (de) 1992-07-15
DE3872737D1 (de) 1992-08-20
JPS63209144A (ja) 1988-08-30
ES2033346T3 (es) 1993-03-16
JP3213711B2 (ja) 2001-10-02
JPH0821701B2 (ja) 1996-03-04
CA1290076C (en) 1991-10-01
BR8800754A (pt) 1988-10-04
EP0283655A3 (en) 1989-11-29
JPH08204162A (ja) 1996-08-09
EP0283655A2 (de) 1988-09-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee