ES2033346T3 - Un metodo de combinar una agrupacion de puertas y circuitos de celulas estandar en una pastilla semiconductora comun. - Google Patents
Un metodo de combinar una agrupacion de puertas y circuitos de celulas estandar en una pastilla semiconductora comun.Info
- Publication number
- ES2033346T3 ES2033346T3 ES198888100942T ES88100942T ES2033346T3 ES 2033346 T3 ES2033346 T3 ES 2033346T3 ES 198888100942 T ES198888100942 T ES 198888100942T ES 88100942 T ES88100942 T ES 88100942T ES 2033346 T3 ES2033346 T3 ES 2033346T3
- Authority
- ES
- Spain
- Prior art keywords
- elements
- doors
- combining
- group
- conductive pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title abstract 2
- SNSBQRXQYMXFJZ-MOKYGWKMSA-N (2s)-6-amino-n-[(2s,3s)-1-amino-3-methyl-1-oxopentan-2-yl]-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-amino-3-phenylpropanoyl]amino]-3-hydroxypropanoyl]amino]propanoyl]amino]-3-hydroxypropanoyl]amino]propanoyl]amino]-4-methylpentanoy Chemical compound CC[C@H](C)[C@@H](C(N)=O)NC(=O)[C@H](CCCCN)NC(=O)[C@H](C)NC(=O)[C@H](CC(C)C)NC(=O)[C@H](C)NC(=O)[C@H](CO)NC(=O)[C@H](C)NC(=O)[C@H](CO)NC(=O)[C@@H](N)CC1=CC=CC=C1 SNSBQRXQYMXFJZ-MOKYGWKMSA-N 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/909—Macrocell arrays, e.g. gate arrays with variable size or configuration of cells
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
SE SUMINISTRA UN METODO Y UNA ESTRUCTURA SEMICONDUCTORA PARA ENTREMEZCLAR CIRCUITOS DE DOS O MAS CLASES DIFERENTES DE ELEMENTOS, TALES COMO ELEMENTOS STARDARD (22, 58) Y ELEMENTOS DE MATRIZ DE PUERTAS LOGICAS (54, 56), SOBRE UN CHIP COMUN O UN SUBSTRATO CON UNA MINIMA SEPARACION ENTRE LOS ELEMENTOS ADYACENTES DE CLASES DIFERENTES. LAS UBICACIONES DE LOS ELEMENTOS SE DEFINEN CON ENLACES DADOS (18) Y DISPUESTOS DE MANERA CONTIGUA SOBRE LA SUPERFICIE DE UN CHIP SEMICONDUCTOR,, Y ASI TANTO LOS TIPOS DE ELEMENTOS STANDARD (22, 58) COMO LOS CIRCUITOS DE TIPO DE MATRIZ DE PUERTAS LOGICAS (54, 56) SE FORMAN DENTRO DE CUALQUIERA DE LOS LUGARES PARA LOS ELEMENTOS SUMINISTRANDO ASI UNA ESTRUCTURA EQUILIBRADORA DE LA DENSIDAD DEL CHIP.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/018,239 US4786613A (en) | 1987-02-24 | 1987-02-24 | Method of combining gate array and standard cell circuits on a common semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2033346T3 true ES2033346T3 (es) | 1993-03-16 |
Family
ID=21786931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES198888100942T Expired - Lifetime ES2033346T3 (es) | 1987-02-24 | 1988-01-22 | Un metodo de combinar una agrupacion de puertas y circuitos de celulas estandar en una pastilla semiconductora comun. |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4786613A (es) |
| EP (1) | EP0283655B1 (es) |
| JP (2) | JPH0821701B2 (es) |
| BR (1) | BR8800754A (es) |
| CA (1) | CA1290076C (es) |
| DE (1) | DE3872737T2 (es) |
| ES (1) | ES2033346T3 (es) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5051917A (en) * | 1987-02-24 | 1991-09-24 | International Business Machines Corporation | Method of combining gate array and standard cell circuits on a common semiconductor chip |
| US4831725A (en) * | 1988-06-10 | 1989-05-23 | International Business Machines Corporation | Global wiring by removal of redundant paths |
| JPH02278848A (ja) * | 1989-04-20 | 1990-11-15 | Nec Corp | 集積回路装置 |
| US5015600A (en) * | 1990-01-25 | 1991-05-14 | Northern Telecom Limited | Method for making integrated circuits |
| JP3027990B2 (ja) * | 1991-03-18 | 2000-04-04 | 富士通株式会社 | 半導体装置の製造方法 |
| WO1993012540A1 (en) * | 1991-12-10 | 1993-06-24 | Vlsi Technology, Inc. | Integrated circuit with variable pad pitch |
| JPH08316331A (ja) * | 1995-03-15 | 1996-11-29 | Toshiba Corp | 半導体集積回路及びその設計方法 |
| FR2741475B1 (fr) * | 1995-11-17 | 2000-05-12 | Commissariat Energie Atomique | Procede de fabrication d'un dispositif de micro-electronique comportant sur un substrat une pluralite d'elements interconnectes |
| TW392307B (en) * | 1998-01-13 | 2000-06-01 | Mitsubishi Electric Corp | A method of the manufacture and the setup of the semiconductor apparatus |
| US6532581B1 (en) | 1998-07-03 | 2003-03-11 | Matsushita Electric Industrial Co., Ltd. | Method for designing layout of semiconductor device, storage medium having stored thereon program for executing the layout designing method, and semiconductor device |
| TW519748B (en) * | 2001-12-26 | 2003-02-01 | Faraday Tech Corp | Semiconductor device with substrate-triggered ESD protection |
| JP2004007472A (ja) * | 2002-03-22 | 2004-01-08 | Toshiba Corp | 半導体集積回路、データ転送システム、及びデータ転送方法 |
| JP2004221231A (ja) * | 2003-01-14 | 2004-08-05 | Nec Electronics Corp | レイアウトパターン生成のための装置と方法、及びそれを用いた半導体装置の製造方法 |
| US7095063B2 (en) * | 2003-05-07 | 2006-08-22 | International Business Machines Corporation | Multiple supply gate array backfill structure |
| DE102004038063A1 (de) * | 2004-07-30 | 2006-03-23 | Infineon Technologies Ag | Verfahren zur Herstellung einer Standardzellenanordnung und eine Vorrichtung zur Durchführung des Verfahrens |
| JP2012064854A (ja) * | 2010-09-17 | 2012-03-29 | Toshiba Corp | 半導体装置 |
| US20210200927A1 (en) * | 2019-12-31 | 2021-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method for Transistor Placement in Standard Cell Layout |
| US11663391B2 (en) | 2021-08-25 | 2023-05-30 | International Business Machines Corporation | Latch-up avoidance for sea-of-gates |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US814122A (en) * | 1904-06-25 | 1906-03-06 | Henry G Eckstein | Apparatus for the manufacture of moisture-proof cartons. |
| JPS5925381B2 (ja) * | 1977-12-30 | 1984-06-16 | 富士通株式会社 | 半導体集積回路装置 |
| JPS5890758A (ja) * | 1981-11-25 | 1983-05-30 | Mitsubishi Electric Corp | 相補形集積回路装置 |
| FR2524206B1 (fr) * | 1982-03-26 | 1985-12-13 | Thomson Csf Mat Tel | Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit |
| US4513307A (en) * | 1982-05-05 | 1985-04-23 | Rockwell International Corporation | CMOS/SOS transistor gate array apparatus |
| JPS5943548A (ja) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | 半導体集積回路装置 |
| JPS60110137A (ja) * | 1983-11-18 | 1985-06-15 | Sanyo Electric Co Ltd | 半導体装置 |
| JPS60177650A (ja) * | 1984-02-23 | 1985-09-11 | Toshiba Corp | 半導体装置およびその製造方法 |
| US4570176A (en) * | 1984-04-16 | 1986-02-11 | At&T Bell Laboratories | CMOS Cell array with transistor isolation |
| JPS60234231A (ja) * | 1984-05-04 | 1985-11-20 | Fuji Photo Film Co Ltd | 磁気記録媒体 |
| JPS60234341A (ja) * | 1984-05-07 | 1985-11-21 | Hitachi Ltd | 半導体集回路装置 |
| JPS6124250A (ja) * | 1984-07-13 | 1986-02-01 | Nippon Gakki Seizo Kk | 半導体集積回路装置 |
| JPS61123153A (ja) * | 1984-11-20 | 1986-06-11 | Fujitsu Ltd | ゲ−トアレイｌｓｉ装置 |
| JPS61202450A (ja) * | 1985-03-05 | 1986-09-08 | Nec Corp | 半導体集積回路装置 |
| JPH0785490B2 (ja) * | 1986-01-22 | 1995-09-13 | 日本電気株式会社 | 集積回路装置 |
-
1987
- 1987-02-24 US US07/018,239 patent/US4786613A/en not_active Expired - Lifetime
- 1987-12-18 JP JP62319139A patent/JPH0821701B2/ja not_active Expired - Lifetime
-
1988
- 1988-01-15 CA CA000556670A patent/CA1290076C/en not_active Expired - Fee Related
- 1988-01-22 EP EP88100942A patent/EP0283655B1/en not_active Expired
- 1988-01-22 DE DE8888100942T patent/DE3872737T2/de not_active Expired - Fee Related
- 1988-01-22 ES ES198888100942T patent/ES2033346T3/es not_active Expired - Lifetime
- 1988-02-23 BR BR8800754A patent/BR8800754A/pt not_active IP Right Cessation
-
1995
- 1995-08-09 JP JP20293995A patent/JP3213711B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0283655A2 (en) | 1988-09-28 |
| EP0283655A3 (en) | 1989-11-29 |
| US4786613A (en) | 1988-11-22 |
| DE3872737D1 (de) | 1992-08-20 |
| DE3872737T2 (de) | 1993-03-04 |
| JPH0821701B2 (ja) | 1996-03-04 |
| JPS63209144A (ja) | 1988-08-30 |
| CA1290076C (en) | 1991-10-01 |
| BR8800754A (pt) | 1988-10-04 |
| EP0283655B1 (en) | 1992-07-15 |
| JP3213711B2 (ja) | 2001-10-02 |
| JPH08204162A (ja) | 1996-08-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG2A | Definitive protection |
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