DE3684638D1 - Fuer einen betriebstest angepasste halbleiterspeicheranordnung. - Google Patents

Fuer einen betriebstest angepasste halbleiterspeicheranordnung.

Info

Publication number
DE3684638D1
DE3684638D1 DE8686304574T DE3684638T DE3684638D1 DE 3684638 D1 DE3684638 D1 DE 3684638D1 DE 8686304574 T DE8686304574 T DE 8686304574T DE 3684638 T DE3684638 T DE 3684638T DE 3684638 D1 DE3684638 D1 DE 3684638D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
operation test
memory arrangement
arrangement adapted
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686304574T
Other languages
English (en)
Inventor
Tetsuji Takeguchi Te Takeguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3684638D1 publication Critical patent/DE3684638D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)
DE8686304574T 1985-06-17 1986-06-13 Fuer einen betriebstest angepasste halbleiterspeicheranordnung. Expired - Fee Related DE3684638D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60131591A JPS61289600A (ja) 1985-06-17 1985-06-17 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3684638D1 true DE3684638D1 (de) 1992-05-07

Family

ID=15061631

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686304574T Expired - Fee Related DE3684638D1 (de) 1985-06-17 1986-06-13 Fuer einen betriebstest angepasste halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4720818A (de)
EP (1) EP0206695B1 (de)
JP (1) JPS61289600A (de)
KR (1) KR900006161B1 (de)
DE (1) DE3684638D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293598A (ja) * 1986-06-12 1987-12-21 Toshiba Corp 半導体記憶装置
FR2622019B1 (fr) * 1987-10-19 1990-02-09 Thomson Semiconducteurs Dispositif de test structurel d'un circuit integre
JPH01113999A (ja) * 1987-10-28 1989-05-02 Toshiba Corp 不揮発性メモリのストレステスト回路
DE68929258T2 (de) * 1988-01-27 2001-06-07 Oki Electric Industry Co., Ltd. Mikrorechner und Prüfverfahren
JPH01208795A (ja) * 1988-02-16 1989-08-22 Toshiba Corp 半導体記憶装置
US5266939A (en) * 1989-01-18 1993-11-30 Mitsubishi Denki Kabushiki Kaisha Memory data synthesizer
JPH02189080A (ja) * 1989-01-18 1990-07-25 Mitsubishi Electric Corp メモリデータ合成装置
US5117426A (en) * 1990-03-26 1992-05-26 Texas Instruments Incorporated Circuit, device, and method to detect voltage leakage
US5181205A (en) * 1990-04-10 1993-01-19 National Semiconductor Corporation Short circuit detector circuit for memory arrays
JPH04119595A (ja) * 1990-09-11 1992-04-21 Toshiba Corp 不揮発性半導体メモリ
KR960007363Y1 (ko) * 1990-10-02 1996-08-28 가부시기가이샤 도오시바 반도체 메모리
JP3237127B2 (ja) * 1991-04-19 2001-12-10 日本電気株式会社 ダイナミックランダムアクセスメモリ装置
DE4223532A1 (de) * 1992-07-17 1994-01-20 Philips Patentverwaltung Schaltungsanordnung zum Prüfen der Adressierung wenigstens einer Matrix
US5392248A (en) * 1993-10-26 1995-02-21 Texas Instruments Incorporated Circuit and method for detecting column-line shorts in integrated-circuit memories
US5508631A (en) * 1994-10-27 1996-04-16 Mitel Corporation Semiconductor test chip with on wafer switching matrix
JP4727785B2 (ja) * 2000-01-26 2011-07-20 富士通セミコンダクター株式会社 半導体記憶装置及び半導体記憶装置のワード線欠陥検出方法
US6992925B2 (en) * 2002-04-26 2006-01-31 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
US7755162B2 (en) 2004-05-06 2010-07-13 Sidense Corp. Anti-fuse memory cell
CA2520140C (en) 2004-05-06 2007-05-15 Sidense Corp. Split-channel antifuse array architecture
US8735297B2 (en) 2004-05-06 2014-05-27 Sidense Corporation Reverse optical proximity correction method
KR100870423B1 (ko) * 2007-06-27 2008-11-26 주식회사 하이닉스반도체 반도체메모리소자
JP7086795B2 (ja) * 2018-09-03 2022-06-20 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4850646A (de) * 1971-10-26 1973-07-17
JPS6042560B2 (ja) * 1981-03-17 1985-09-24 日本電信電話株式会社 半導体記憶装置
JPS595498A (ja) * 1982-07-01 1984-01-12 Fujitsu Ltd 読出し専用の半導体記憶装置
JPS6085800U (ja) * 1983-11-18 1985-06-13 日本電気株式会社 半導体読出し専用メモリ

Also Published As

Publication number Publication date
US4720818A (en) 1988-01-19
EP0206695A3 (en) 1989-12-06
EP0206695A2 (de) 1986-12-30
JPS61289600A (ja) 1986-12-19
KR870000708A (ko) 1987-02-20
EP0206695B1 (de) 1992-04-01
KR900006161B1 (ko) 1990-08-24
JPH0451919B2 (de) 1992-08-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee