DE3689031D1 - Integrierte Halbleiterschaltung mit Prüfschaltung. - Google Patents

Integrierte Halbleiterschaltung mit Prüfschaltung.

Info

Publication number
DE3689031D1
DE3689031D1 DE86402572T DE3689031T DE3689031D1 DE 3689031 D1 DE3689031 D1 DE 3689031D1 DE 86402572 T DE86402572 T DE 86402572T DE 3689031 T DE3689031 T DE 3689031T DE 3689031 D1 DE3689031 D1 DE 3689031D1
Authority
DE
Germany
Prior art keywords
circuit
integrated semiconductor
test
test circuit
semiconductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE86402572T
Other languages
English (en)
Other versions
DE3689031T2 (de
Inventor
Tetsu Tanizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60258472A external-priority patent/JPS62229867A/ja
Priority claimed from JP60258469A external-priority patent/JP2557833B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3689031D1 publication Critical patent/DE3689031D1/de
Publication of DE3689031T2 publication Critical patent/DE3689031T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
DE86402572T 1985-11-20 1986-11-20 Integrierte Halbleiterschaltung mit Prüfschaltung. Expired - Fee Related DE3689031T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60258472A JPS62229867A (ja) 1985-11-20 1985-11-20 試験回路を有する半導体集積回路装置
JP60258469A JP2557833B2 (ja) 1985-11-20 1985-11-20 試験回路を有する半導体集積回路装置及びその試験方法

Publications (2)

Publication Number Publication Date
DE3689031D1 true DE3689031D1 (de) 1993-10-21
DE3689031T2 DE3689031T2 (de) 1994-01-27

Family

ID=26543690

Family Applications (1)

Application Number Title Priority Date Filing Date
DE86402572T Expired - Fee Related DE3689031T2 (de) 1985-11-20 1986-11-20 Integrierte Halbleiterschaltung mit Prüfschaltung.

Country Status (4)

Country Link
US (1) US4739250A (de)
EP (1) EP0223714B1 (de)
KR (1) KR900006048B1 (de)
DE (1) DE3689031T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868823B1 (en) * 1984-08-31 1999-07-06 Texas Instruments Inc High speed concurrent testing of dynamic read/write memory array
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
JPS63217821A (ja) * 1987-03-06 1988-09-09 Toshiba Corp 半導体集積回路
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
US4937826A (en) * 1988-09-09 1990-06-26 Crosscheck Technology, Inc. Method and apparatus for sensing defects in integrated circuit elements
GB8827629D0 (en) * 1988-11-25 1988-12-29 Lsi Logic Europ Testing of analogue circuits
GB8921561D0 (en) * 1989-09-23 1989-11-08 Univ Edinburgh Designs and procedures for testing integrated circuits containing sensor arrays
GB2253710B (en) * 1989-09-23 1993-08-25 Univ Edinburgh Test circuit
DE69027828T2 (de) * 1989-10-13 1996-11-21 Fujitsu Ltd Integrierte Halbleiter-Schaltungs-Vorrichtungen
JP2612618B2 (ja) * 1989-10-13 1997-05-21 富士通株式会社 半導体集積回路装置
JPH03270251A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd 半導体集積回路装置
US5157627A (en) * 1990-07-17 1992-10-20 Crosscheck Technology, Inc. Method and apparatus for setting desired signal level on storage element
US5341383A (en) * 1990-07-30 1994-08-23 Fujitsu Limited Circuit arrangement suitable for testing cells arranged in rows and columns, semiconductor integrated circuit device having the same, and method for arranging circuit blocks on chip
US5199035A (en) * 1990-10-01 1993-03-30 Motorola, Inc. Logic circuit for reliability and yield enhancement
US5179534A (en) * 1990-10-23 1993-01-12 Crosscheck Technology, Inc. Method and apparatus for setting desired logic state at internal point of a select storage element
US5230001A (en) * 1991-03-08 1993-07-20 Crosscheck Technology, Inc. Method for testing a sequential circuit by splicing test vectors into sequential test pattern
US5206862A (en) * 1991-03-08 1993-04-27 Crosscheck Technology, Inc. Method and apparatus for locally deriving test signals from previous response signals
US5872448A (en) * 1991-06-18 1999-02-16 Lightspeed Semiconductor Corporation Integrated circuit architecture having an array of test cells providing full controlability for automatic circuit verification
JP2884847B2 (ja) * 1991-10-03 1999-04-19 三菱電機株式会社 故障検出機能を備えた半導体集積回路装置の製造方法
US5530814A (en) * 1991-10-30 1996-06-25 I-Cube, Inc. Bi-directional crossbar switch with control memory for selectively routing signals between pairs of signal ports
US5347519A (en) * 1991-12-03 1994-09-13 Crosspoint Solutions Inc. Preprogramming testing in a field programmable gate array
US5442282A (en) * 1992-07-02 1995-08-15 Lsi Logic Corporation Testing and exercising individual, unsingulated dies on a wafer
US5389556A (en) * 1992-07-02 1995-02-14 Lsi Logic Corporation Individually powering-up unsingulated dies on a wafer
US5648661A (en) * 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5495486A (en) * 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
CH688425A5 (fr) * 1993-05-24 1997-09-15 Suisse Electronique Microtech Circuit électronique organisé en réseau matriciel de cellules.
JPH07159496A (ja) * 1993-10-12 1995-06-23 At & T Global Inf Solutions Internatl Inc 集積回路の検査のための装置及びその方法
US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer
US6108804A (en) * 1997-09-11 2000-08-22 Micron Technology, Inc. Method and apparatus for testing adjustment of a circuit parameter

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3958110A (en) * 1974-12-18 1976-05-18 Ibm Corporation Logic array with testing circuitry
JPH07119789B2 (ja) * 1983-02-04 1995-12-20 株式会社日立製作所 半導体集積回路装置及びその診断方法
US4499579A (en) * 1983-03-10 1985-02-12 Honeywell Information Systems Inc. Programmable logic array with dynamic test capability in the unprogrammed state
JPS6088370A (ja) * 1983-10-20 1985-05-18 Toshiba Corp 論理回路
JPH073865B2 (ja) * 1984-08-07 1995-01-18 富士通株式会社 半導体集積回路及び半導体集積回路の試験方法

Also Published As

Publication number Publication date
EP0223714A2 (de) 1987-05-27
EP0223714B1 (de) 1993-09-15
US4739250A (en) 1988-04-19
KR900006048B1 (ko) 1990-08-20
DE3689031T2 (de) 1994-01-27
KR870005516A (ko) 1987-06-09
EP0223714A3 (en) 1988-09-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee