DE3512841A1 - Heterouebergang-bipolartransistor mit planarstruktur und verfahren zu seiner herstellung - Google Patents

Heterouebergang-bipolartransistor mit planarstruktur und verfahren zu seiner herstellung

Info

Publication number
DE3512841A1
DE3512841A1 DE19853512841 DE3512841A DE3512841A1 DE 3512841 A1 DE3512841 A1 DE 3512841A1 DE 19853512841 DE19853512841 DE 19853512841 DE 3512841 A DE3512841 A DE 3512841A DE 3512841 A1 DE3512841 A1 DE 3512841A1
Authority
DE
Germany
Prior art keywords
zone
collector
base
emitter
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19853512841
Other languages
German (de)
English (en)
Other versions
DE3512841C2 (enExample
Inventor
Masao Machida Tokio/Tokyo Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3512841A1 publication Critical patent/DE3512841A1/de
Application granted granted Critical
Publication of DE3512841C2 publication Critical patent/DE3512841C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
DE19853512841 1984-05-29 1985-04-10 Heterouebergang-bipolartransistor mit planarstruktur und verfahren zu seiner herstellung Granted DE3512841A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59108794A JPS60253267A (ja) 1984-05-29 1984-05-29 ヘテロ接合バイポ−ラトランジスタおよびその製造方法

Publications (2)

Publication Number Publication Date
DE3512841A1 true DE3512841A1 (de) 1985-12-05
DE3512841C2 DE3512841C2 (enExample) 1989-12-28

Family

ID=14493646

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853512841 Granted DE3512841A1 (de) 1984-05-29 1985-04-10 Heterouebergang-bipolartransistor mit planarstruktur und verfahren zu seiner herstellung

Country Status (2)

Country Link
JP (1) JPS60253267A (enExample)
DE (1) DE3512841A1 (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3715232A1 (de) * 1987-05-07 1988-11-17 Siemens Ag Verfahren zur substratkontaktierung bei der herstellung von durch isolationsgraeben getrennten bipolartransistorschaltungen
US4983532A (en) * 1987-12-23 1991-01-08 Hitachi, Ltd. Process for fabricating heterojunction bipolar transistors
EP0416166A1 (de) * 1989-09-08 1991-03-13 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Heterobipolartransistors mit Separation des Kollektoranschlusses
EP0460285A3 (en) * 1990-06-07 1992-12-30 Siemens Aktiengesellschaft Process for manufacturing bipolar transistors with an extremely reduced base-collector capacitance
DE3736693C2 (de) * 1986-10-29 2001-10-18 Sony Corp Bipolarer Transistor mit Heteroübergang

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159774A (ja) * 1984-08-30 1986-03-27 Fujitsu Ltd 半導体装置の製造方法
US4672414A (en) * 1985-06-28 1987-06-09 Texas Instruments Incorporated Planar heterojunction bipolar device and method
JPH0713968B2 (ja) * 1986-01-07 1995-02-15 富士通株式会社 化合物半導体装置の製造方法
JP2615646B2 (ja) * 1987-08-11 1997-06-04 ソニー株式会社 バイポーラトランジスタの製造方法
JPH0210734A (ja) * 1988-06-29 1990-01-16 Sony Corp 半導体装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4044452A (en) * 1976-10-06 1977-08-30 International Business Machines Corporation Process for making field effect and bipolar transistors on the same semiconductor chip
US4086694A (en) * 1975-05-19 1978-05-02 International Telephone & Telegraph Corporation Method of making direct metal contact to buried layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024592B2 (ja) * 1975-01-27 1985-06-13 株式会社日立製作所 ワイドギヤツプエミツタトランジスタの製造方法
JPS5658258A (en) * 1979-10-16 1981-05-21 Mitsubishi Electric Corp Semiconductor integrated circuit
JPS6048909B2 (ja) * 1981-05-29 1985-10-30 富士通株式会社 能動的半導体装置及び製造方法
JPS59208873A (ja) * 1983-05-13 1984-11-27 Agency Of Ind Science & Technol 半導体装置
JPS60177671A (ja) * 1984-02-24 1985-09-11 Fujitsu Ltd ヘテロ接合バイポ−ラ半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4086694A (en) * 1975-05-19 1978-05-02 International Telephone & Telegraph Corporation Method of making direct metal contact to buried layer
US4044452A (en) * 1976-10-06 1977-08-30 International Business Machines Corporation Process for making field effect and bipolar transistors on the same semiconductor chip

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ASBECK, Peter M. et al: 4.5 GHz Frequency Dividers using GaAs/(GaAl) as Heterojunction Bipolar Transistors. In: IEEE International Solid-State Circuits Conference, 22. Feb. 1984, S. 50-51 *
Electronics Letters, 1983, Vol. 19, Nr. 10, S. 367-368 *
PAN, P.H., TSANG, P.J.: Bird's Beak-Free Recessed Oxide Isolation By O¶2¶ Ion Implantation. In: IBM Technical Disclosure Bulletin, 1983, Vol. 26, Nr. 2, S. 621-622 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3736693C2 (de) * 1986-10-29 2001-10-18 Sony Corp Bipolarer Transistor mit Heteroübergang
DE3715232A1 (de) * 1987-05-07 1988-11-17 Siemens Ag Verfahren zur substratkontaktierung bei der herstellung von durch isolationsgraeben getrennten bipolartransistorschaltungen
US4983532A (en) * 1987-12-23 1991-01-08 Hitachi, Ltd. Process for fabricating heterojunction bipolar transistors
EP0416166A1 (de) * 1989-09-08 1991-03-13 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Heterobipolartransistors mit Separation des Kollektoranschlusses
EP0460285A3 (en) * 1990-06-07 1992-12-30 Siemens Aktiengesellschaft Process for manufacturing bipolar transistors with an extremely reduced base-collector capacitance

Also Published As

Publication number Publication date
JPS60253267A (ja) 1985-12-13
DE3512841C2 (enExample) 1989-12-28

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee