DE2818525A1 - Verfahren zum herstellen einer integrierten halbleiterschaltung - Google Patents

Verfahren zum herstellen einer integrierten halbleiterschaltung

Info

Publication number
DE2818525A1
DE2818525A1 DE19782818525 DE2818525A DE2818525A1 DE 2818525 A1 DE2818525 A1 DE 2818525A1 DE 19782818525 DE19782818525 DE 19782818525 DE 2818525 A DE2818525 A DE 2818525A DE 2818525 A1 DE2818525 A1 DE 2818525A1
Authority
DE
Germany
Prior art keywords
layer
areas
photoresist
polysilicon
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19782818525
Other languages
German (de)
English (en)
Inventor
Madhukar Laxman Joshi
Paul Franz-Josef Landler
Ronald Silverman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2818525A1 publication Critical patent/DE2818525A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10W20/01—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE19782818525 1977-05-02 1978-04-27 Verfahren zum herstellen einer integrierten halbleiterschaltung Withdrawn DE2818525A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/793,217 US4123300A (en) 1977-05-02 1977-05-02 Integrated circuit process utilizing lift-off techniques

Publications (1)

Publication Number Publication Date
DE2818525A1 true DE2818525A1 (de) 1978-11-09

Family

ID=25159410

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782818525 Withdrawn DE2818525A1 (de) 1977-05-02 1978-04-27 Verfahren zum herstellen einer integrierten halbleiterschaltung

Country Status (8)

Country Link
US (1) US4123300A (enExample)
JP (1) JPS5856267B2 (enExample)
DE (1) DE2818525A1 (enExample)
FR (1) FR2390007B1 (enExample)
GB (1) GB1600048A (enExample)
IT (1) IT1112624B (enExample)
NL (1) NL7804517A (enExample)
SE (1) SE7804921L (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3131240A1 (de) * 1980-08-15 1982-06-09 Hitachi, Ltd., Tokyo Halbleitervorrichtungen und verfahren zu ihrer herstellung

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4305760A (en) * 1978-12-22 1981-12-15 Ncr Corporation Polysilicon-to-substrate contact processing
JPS6043656B2 (ja) * 1979-06-06 1985-09-30 株式会社東芝 半導体装置の製造方法
US4240845A (en) * 1980-02-04 1980-12-23 International Business Machines Corporation Method of fabricating random access memory device
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
US4358326A (en) * 1980-11-03 1982-11-09 International Business Machines Corporation Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing
US4814285A (en) * 1985-09-23 1989-03-21 Harris Corp. Method for forming planarized interconnect level using selective deposition and ion implantation
US5075817A (en) * 1990-06-22 1991-12-24 Ramtron Corporation Trench capacitor for large scale integrated memory
US5104822A (en) * 1990-07-30 1992-04-14 Ramtron Corporation Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3847687A (en) * 1972-11-15 1974-11-12 Motorola Inc Methods of forming self aligned transistor structure having polycrystalline contacts
GB1444047A (en) * 1973-02-28 1976-07-28 Hitachi Ltd Charge transfer semiconductor devices and methods of fabricating such devices
US4055885A (en) * 1973-02-28 1977-11-01 Hitachi, Ltd. Charge transfer semiconductor device with electrodes separated by oxide region therebetween and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3131240A1 (de) * 1980-08-15 1982-06-09 Hitachi, Ltd., Tokyo Halbleitervorrichtungen und verfahren zu ihrer herstellung
US5028975A (en) * 1980-08-15 1991-07-02 Hitachi, Ltd. Semiconductor devices and a process for producing the same

Also Published As

Publication number Publication date
FR2390007B1 (enExample) 1982-05-14
NL7804517A (nl) 1978-11-06
IT7822794A0 (it) 1978-04-28
FR2390007A1 (enExample) 1978-12-01
GB1600048A (en) 1981-10-14
JPS5856267B2 (ja) 1983-12-14
SE7804921L (sv) 1978-11-03
IT1112624B (it) 1986-01-20
JPS53136494A (en) 1978-11-29
US4123300A (en) 1978-10-31

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee