IT7822794A0 - Processo di fabbricazione di circuiti integrati. - Google Patents

Processo di fabbricazione di circuiti integrati.

Info

Publication number
IT7822794A0
IT7822794A0 IT7822794A IT2279478A IT7822794A0 IT 7822794 A0 IT7822794 A0 IT 7822794A0 IT 7822794 A IT7822794 A IT 7822794A IT 2279478 A IT2279478 A IT 2279478A IT 7822794 A0 IT7822794 A0 IT 7822794A0
Authority
IT
Italy
Prior art keywords
manufacturing process
integrated circuits
circuits manufacturing
integrated
manufacturing
Prior art date
Application number
IT7822794A
Other languages
English (en)
Other versions
IT1112624B (it
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT7822794A0 publication Critical patent/IT7822794A0/it
Application granted granted Critical
Publication of IT1112624B publication Critical patent/IT1112624B/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT22794/78A 1977-05-02 1978-04-28 Processo di fabbricazione di circuiti integrati IT1112624B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/793,217 US4123300A (en) 1977-05-02 1977-05-02 Integrated circuit process utilizing lift-off techniques

Publications (2)

Publication Number Publication Date
IT7822794A0 true IT7822794A0 (it) 1978-04-28
IT1112624B IT1112624B (it) 1986-01-20

Family

ID=25159410

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22794/78A IT1112624B (it) 1977-05-02 1978-04-28 Processo di fabbricazione di circuiti integrati

Country Status (8)

Country Link
US (1) US4123300A (it)
JP (1) JPS5856267B2 (it)
DE (1) DE2818525A1 (it)
FR (1) FR2390007B1 (it)
GB (1) GB1600048A (it)
IT (1) IT1112624B (it)
NL (1) NL7804517A (it)
SE (1) SE7804921L (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4305760A (en) * 1978-12-22 1981-12-15 Ncr Corporation Polysilicon-to-substrate contact processing
JPS6043656B2 (ja) * 1979-06-06 1985-09-30 株式会社東芝 半導体装置の製造方法
US4240845A (en) * 1980-02-04 1980-12-23 International Business Machines Corporation Method of fabricating random access memory device
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
US4358326A (en) * 1980-11-03 1982-11-09 International Business Machines Corporation Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing
US4814285A (en) * 1985-09-23 1989-03-21 Harris Corp. Method for forming planarized interconnect level using selective deposition and ion implantation
US5075817A (en) * 1990-06-22 1991-12-24 Ramtron Corporation Trench capacitor for large scale integrated memory
US5104822A (en) * 1990-07-30 1992-04-14 Ramtron Corporation Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3847687A (en) * 1972-11-15 1974-11-12 Motorola Inc Methods of forming self aligned transistor structure having polycrystalline contacts
US4055885A (en) * 1973-02-28 1977-11-01 Hitachi, Ltd. Charge transfer semiconductor device with electrodes separated by oxide region therebetween and method for fabricating the same
GB1444047A (en) * 1973-02-28 1976-07-28 Hitachi Ltd Charge transfer semiconductor devices and methods of fabricating such devices

Also Published As

Publication number Publication date
JPS53136494A (en) 1978-11-29
FR2390007B1 (it) 1982-05-14
IT1112624B (it) 1986-01-20
JPS5856267B2 (ja) 1983-12-14
SE7804921L (sv) 1978-11-03
NL7804517A (nl) 1978-11-06
US4123300A (en) 1978-10-31
GB1600048A (en) 1981-10-14
DE2818525A1 (de) 1978-11-09
FR2390007A1 (it) 1978-12-01

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