IT7819249A0 - Circuiti integrati. - Google Patents

Circuiti integrati.

Info

Publication number
IT7819249A0
IT7819249A0 IT7819249A IT1924978A IT7819249A0 IT 7819249 A0 IT7819249 A0 IT 7819249A0 IT 7819249 A IT7819249 A IT 7819249A IT 1924978 A IT1924978 A IT 1924978A IT 7819249 A0 IT7819249 A0 IT 7819249A0
Authority
IT
Italy
Prior art keywords
integrated circuits
circuits
integrated
Prior art date
Application number
IT7819249A
Other languages
English (en)
Other versions
IT1091814B (it
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of IT7819249A0 publication Critical patent/IT7819249A0/it
Application granted granted Critical
Publication of IT1091814B publication Critical patent/IT1091814B/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883Combination of depletion and enhancement field effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096Synchronous circuits, i.e. using clock signals
IT19249/78A 1977-01-17 1978-01-13 Circutti integrati IT1091814B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1788/77A GB1575741A (en) 1977-01-17 1977-01-17 Integrated circuits

Publications (2)

Publication Number Publication Date
IT7819249A0 true IT7819249A0 (it) 1978-01-13
IT1091814B IT1091814B (it) 1985-07-06

Family

ID=9728014

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19249/78A IT1091814B (it) 1977-01-17 1978-01-13 Circutti integrati

Country Status (16)

Country Link
US (1) US4218693A (it)
JP (1) JPS5390778A (it)
AR (1) AR215918A1 (it)
AU (1) AU511541B2 (it)
BE (1) BE862950A (it)
BR (1) BR7800236A (it)
CA (1) CA1112306A (it)
CH (1) CH616023A5 (it)
DD (1) DD136674A5 (it)
DE (1) DE2801285C2 (it)
FR (1) FR2377707A1 (it)
GB (1) GB1575741A (it)
IT (1) IT1091814B (it)
MX (1) MX144143A (it)
NL (1) NL188433C (it)
SE (1) SE434203B (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0039736A4 (en) * 1979-11-14 1983-04-06 Ncr Corp CONDUCTOR-INSULATION-SEMICONDUCTOR DEVICES AND THEIR MANUFACTURING METHOD.
US4319396A (en) * 1979-12-28 1982-03-16 Bell Telephone Laboratories, Incorporated Method for fabricating IGFET integrated circuits
NL8003519A (nl) * 1980-06-18 1982-01-18 Philips Nv Lekstroomcompensatie voor dynamische mos logica.
DE3047222A1 (de) * 1980-12-15 1982-07-15 Naamloze Vennootschap Philips' Gloeilampenfabrieken, 5621 Eindhoven Verknuepfungsschaltung in 2-phasen-mos-technik
GB2120029B (en) * 1982-05-12 1985-10-23 Philips Electronic Associated Dynamic two-phase circuit arrangement
US4511914A (en) * 1982-07-01 1985-04-16 Motorola, Inc. Power bus routing for providing noise isolation in gate arrays
US5184202A (en) * 1983-07-27 1993-02-02 Hitachi, Ltd. Semiconductor integrated circuit device
JPH073862B2 (ja) * 1983-07-27 1995-01-18 株式会社日立製作所 半導体記憶装置
US4686629A (en) * 1984-05-10 1987-08-11 Rca Corporation Logic cell placement method in computer-aided-customization of universal arrays and resulting integrated circuit
JPH0620301U (ja) * 1992-04-24 1994-03-15 鉄巳 藤山 組立て式簡易ごみ箱
US10275560B2 (en) * 2016-05-26 2019-04-30 Synopsys, Inc. Placement of circuit elements in regions with customized placement grids

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2348984A1 (de) * 1973-09-28 1975-04-24 Siemens Ag Anordnung mit feldeffekttransistoren
US4037242A (en) * 1975-12-29 1977-07-19 Texas Instruments Incorporated Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device
US4075045A (en) * 1976-02-09 1978-02-21 International Business Machines Corporation Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps
US4107548A (en) * 1976-03-05 1978-08-15 Hitachi, Ltd. Ratioless type MIS logic circuit
US4110776A (en) * 1976-09-27 1978-08-29 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM

Also Published As

Publication number Publication date
JPS5390778A (en) 1978-08-09
AR215918A1 (es) 1979-11-15
US4218693A (en) 1980-08-19
FR2377707A1 (fr) 1978-08-11
BR7800236A (pt) 1978-10-10
GB1575741A (en) 1980-09-24
SE7800389L (sv) 1978-07-18
NL7800409A (nl) 1978-07-19
AU3242978A (en) 1979-07-19
CH616023A5 (it) 1980-02-29
DD136674A5 (de) 1979-07-18
BE862950A (fr) 1978-07-17
SE434203B (sv) 1984-07-09
NL188433B (nl) 1992-01-16
MX144143A (es) 1981-08-31
IT1091814B (it) 1985-07-06
DE2801285A1 (de) 1978-07-20
CA1112306A (en) 1981-11-10
DE2801285C2 (de) 1982-09-30
FR2377707B1 (it) 1983-07-22
NL188433C (nl) 1992-06-16
JPH0237101B2 (it) 1990-08-22
AU511541B2 (en) 1980-08-21

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960130