EP0039736A4 - Conductor-insulator semiconductor devices and methods for making the same. - Google Patents

Conductor-insulator semiconductor devices and methods for making the same.

Info

Publication number
EP0039736A4
EP0039736A4 EP19800902383 EP80902383A EP0039736A4 EP 0039736 A4 EP0039736 A4 EP 0039736A4 EP 19800902383 EP19800902383 EP 19800902383 EP 80902383 A EP80902383 A EP 80902383A EP 0039736 A4 EP0039736 A4 EP 0039736A4
Authority
EP
European Patent Office
Prior art keywords
conductor
making
methods
same
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP19800902383
Other languages
German (de)
French (fr)
Other versions
EP0039736A1 (en
Inventor
Philip A Dalton Jr
Lowell Carles Bergstedt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of EP0039736A1 publication Critical patent/EP0039736A1/en
Publication of EP0039736A4 publication Critical patent/EP0039736A4/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
EP19800902383 1979-11-14 1980-11-12 Conductor-insulator semiconductor devices and methods for making the same. Ceased EP0039736A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9412179A 1979-11-14 1979-11-14
US94121 1979-11-14

Publications (2)

Publication Number Publication Date
EP0039736A1 EP0039736A1 (en) 1981-11-18
EP0039736A4 true EP0039736A4 (en) 1983-04-06

Family

ID=22243186

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19800902383 Ceased EP0039736A4 (en) 1979-11-14 1980-11-12 Conductor-insulator semiconductor devices and methods for making the same.

Country Status (3)

Country Link
EP (1) EP0039736A4 (en)
JP (1) JPS56501509A (en)
WO (1) WO1981001485A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049520A (en) * 1990-06-06 1991-09-17 Micron Technology, Inc. Method of partially eliminating the bird's beak effect without adding any process steps

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2137592A1 (en) * 1971-05-08 1972-12-29 Matsushita Electric Ind Co Ltd
FR2321194A1 (en) * 1975-08-14 1977-03-11 Nippon Telegraph & Telephone FIELD-EFFECT TRANSISTOR WITH ISOLATED TRIGGER
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
DE2911726A1 (en) * 1978-03-27 1979-10-11 Ncr Co Narrow channel FET mfr. - includes etching field oxide beneath photoresist mask to form wide aperture through which substrate is depletion implanted

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1575741A (en) * 1977-01-17 1980-09-24 Philips Electronic Associated Integrated circuits
US4212683A (en) * 1978-03-27 1980-07-15 Ncr Corporation Method for making narrow channel FET
US4229755A (en) * 1978-08-15 1980-10-21 Rockwell International Corporation Fabrication of very large scale integrated circuits containing N-channel silicon gate nonvolatile memory elements

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2137592A1 (en) * 1971-05-08 1972-12-29 Matsushita Electric Ind Co Ltd
FR2321194A1 (en) * 1975-08-14 1977-03-11 Nippon Telegraph & Telephone FIELD-EFFECT TRANSISTOR WITH ISOLATED TRIGGER
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
DE2911726A1 (en) * 1978-03-27 1979-10-11 Ncr Co Narrow channel FET mfr. - includes etching field oxide beneath photoresist mask to form wide aperture through which substrate is depletion implanted

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO8101485A1 *

Also Published As

Publication number Publication date
JPS56501509A (en) 1981-10-15
WO1981001485A1 (en) 1981-05-28
EP0039736A1 (en) 1981-11-18

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE GB NL

17P Request for examination filed

Effective date: 19811017

DET De: translation of patent claims
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 19850204

RIN1 Information on inventor provided before grant (corrected)

Inventor name: BERGSTEDT, LOWELL CARLES

Inventor name: DALTON, PHILIP A., JR.