IT1072436B - Metodo di fabbricazione di circuiti integrati - Google Patents

Metodo di fabbricazione di circuiti integrati

Info

Publication number
IT1072436B
IT1072436B IT27686/76A IT2768676A IT1072436B IT 1072436 B IT1072436 B IT 1072436B IT 27686/76 A IT27686/76 A IT 27686/76A IT 2768676 A IT2768676 A IT 2768676A IT 1072436 B IT1072436 B IT 1072436B
Authority
IT
Italy
Prior art keywords
integrated circuit
circuit manufacturing
manufacturing
integrated
circuit
Prior art date
Application number
IT27686/76A
Other languages
English (en)
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Application granted granted Critical
Publication of IT1072436B publication Critical patent/IT1072436B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/926—Elongated lead extending axially through another elongated lead

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
IT27686/76A 1975-10-01 1976-09-27 Metodo di fabbricazione di circuiti integrati IT1072436B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/618,717 US4032373A (en) 1975-10-01 1975-10-01 Method of manufacturing dielectrically isolated semiconductive device

Publications (1)

Publication Number Publication Date
IT1072436B true IT1072436B (it) 1985-04-10

Family

ID=24478852

Family Applications (1)

Application Number Title Priority Date Filing Date
IT27686/76A IT1072436B (it) 1975-10-01 1976-09-27 Metodo di fabbricazione di circuiti integrati

Country Status (8)

Country Link
US (1) US4032373A (it)
JP (1) JPS5244189A (it)
CA (1) CA1051123A (it)
DE (1) DE2643016A1 (it)
FR (1) FR2326779A1 (it)
GB (1) GB1527804A (it)
IT (1) IT1072436B (it)
NL (1) NL7610851A (it)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4139442A (en) 1977-09-13 1979-02-13 International Business Machines Corporation Reactive ion etching method for producing deep dielectric isolation in silicon
US4233671A (en) * 1979-01-05 1980-11-11 Stanford University Read only memory and integrated circuit and method of programming by laser means
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
FR2491714A1 (fr) * 1980-10-06 1982-04-09 Radiotechnique Compelec Dispositif semi-conducteur a diodes electroluminescentes localisees et son procede de fabrication
US4491486A (en) * 1981-09-17 1985-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
JPS58105551A (ja) * 1981-11-20 1983-06-23 Fujitsu Ltd 半導体装置
JPS63101992A (ja) * 1986-10-17 1988-05-06 松下冷機株式会社 カ−ドエンコ−ダ
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
JPH0547685A (ja) * 1991-08-07 1993-02-26 Rohm Co Ltd 半導体ウエハへの不純物拡散方法
US6448629B2 (en) * 1999-07-29 2002-09-10 International Business Machines Corporation Semiconductor device and method of making same
US7507440B2 (en) * 2005-02-23 2009-03-24 Ppg Industries Ohio, Inc. Methods of forming composite coatings
EP1804522A1 (en) 2005-12-27 2007-07-04 3M Innovative Properties Company A wire guide plate and a telecommunications module having a wire guide plate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3005937A (en) * 1958-08-21 1961-10-24 Rca Corp Semiconductor signal translating devices
US3768150A (en) * 1970-02-13 1973-10-30 B Sloan Integrated circuit process utilizing orientation dependent silicon etch
US3796612A (en) * 1971-08-05 1974-03-12 Scient Micro Syst Inc Semiconductor isolation method utilizing anisotropic etching and differential thermal oxidation
US3928091A (en) * 1971-09-27 1975-12-23 Hitachi Ltd Method for manufacturing a semiconductor device utilizing selective oxidation
US3930300A (en) * 1973-04-04 1976-01-06 Harris Corporation Junction field effect transistor
FR2252638B1 (it) * 1973-11-23 1978-08-04 Commissariat Energie Atomique
US3892608A (en) * 1974-02-28 1975-07-01 Motorola Inc Method for filling grooves and moats used on semiconductor devices

Also Published As

Publication number Publication date
DE2643016A1 (de) 1977-04-07
CA1051123A (en) 1979-03-20
JPH0145224B2 (it) 1989-10-03
JPS5244189A (en) 1977-04-06
FR2326779A1 (fr) 1977-04-29
GB1527804A (en) 1978-10-11
NL7610851A (nl) 1977-04-05
FR2326779B1 (it) 1980-12-12
US4032373A (en) 1977-06-28

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