IT1063554B - Procedimento per la fabbricazione di circuiti integrati - Google Patents

Procedimento per la fabbricazione di circuiti integrati

Info

Publication number
IT1063554B
IT1063554B IT23631/76A IT2363176A IT1063554B IT 1063554 B IT1063554 B IT 1063554B IT 23631/76 A IT23631/76 A IT 23631/76A IT 2363176 A IT2363176 A IT 2363176A IT 1063554 B IT1063554 B IT 1063554B
Authority
IT
Italy
Prior art keywords
procedure
manufacture
integrated circuits
circuits
integrated
Prior art date
Application number
IT23631/76A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1063554B publication Critical patent/IT1063554B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H10W10/0124—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves the regions having non-rectangular shapes, e.g. rounded
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking
IT23631/76A 1975-06-30 1976-05-26 Procedimento per la fabbricazione di circuiti integrati IT1063554B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/592,014 US3966514A (en) 1975-06-30 1975-06-30 Method for forming dielectric isolation combining dielectric deposition and thermal oxidation

Publications (1)

Publication Number Publication Date
IT1063554B true IT1063554B (it) 1985-02-11

Family

ID=24368919

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23631/76A IT1063554B (it) 1975-06-30 1976-05-26 Procedimento per la fabbricazione di circuiti integrati

Country Status (7)

Country Link
US (1) US3966514A (it)
JP (1) JPS525289A (it)
CA (1) CA1041227A (it)
DE (1) DE2626738C2 (it)
FR (1) FR2316733A1 (it)
GB (1) GB1487547A (it)
IT (1) IT1063554B (it)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038110A (en) * 1974-06-17 1977-07-26 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
DE2529598C3 (de) * 1975-07-02 1978-05-24 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer monolithisch integrierten Halbleiterschaltung mit bipolaren Transistoren
CA1090006A (en) * 1976-12-27 1980-11-18 Wolfgang M. Feist Semiconductor structures and methods for manufacturing such structures
US4149915A (en) * 1978-01-27 1979-04-17 International Business Machines Corporation Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions
JPS54115085A (en) * 1978-02-28 1979-09-07 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
US4271583A (en) * 1980-03-10 1981-06-09 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor devices having planar recessed oxide isolation region
US4318759A (en) * 1980-07-21 1982-03-09 Data General Corporation Retro-etch process for integrated circuits
EP0052948A1 (en) * 1980-11-24 1982-06-02 Motorola, Inc. Oxide isolation process
EP0055521B1 (en) * 1980-11-29 1985-05-22 Kabushiki Kaisha Toshiba Method of filling a groove in a semiconductor substrate
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
JPS5970964U (ja) * 1982-11-05 1984-05-14 三菱自動車工業株式会社 Ｏ−リングの固定構造
JPS59139643A (ja) * 1983-01-31 1984-08-10 Hitachi Ltd 半導体装置およびその製造方法
US4561172A (en) * 1984-06-15 1985-12-31 Texas Instruments Incorporated Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions
US4538343A (en) * 1984-06-15 1985-09-03 Texas Instruments Incorporated Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
US4749662A (en) * 1984-12-14 1988-06-07 Rockwell International Corporation Diffused field CMOS-bulk process
US4631219A (en) * 1985-01-31 1986-12-23 International Business Machines Corporation Growth of bird's beak free semi-rox
JPS6281727A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd 埋込型素子分離溝の形成方法
JPS63234548A (ja) * 1987-03-24 1988-09-29 Oki Electric Ind Co Ltd 半導体素子の製造方法
US4814290A (en) * 1987-10-30 1989-03-21 International Business Machines Corporation Method for providing increased dopant concentration in selected regions of semiconductor devices
US4948456A (en) * 1989-06-09 1990-08-14 Delco Electronics Corporation Confined lateral selective epitaxial growth
KR102434436B1 (ko) * 2017-05-31 2022-08-19 삼성전자주식회사 집적회로 소자 및 그 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH516871A (it) * 1969-07-30 1971-12-15 Soc Gen Semiconduttori Spa Procedimento per ottenere dispositivi a semiconduttore con minimi dislivelli in superficie, e dispositivo a semiconduttore ottenuto mediante detto procedimento
US3681153A (en) * 1970-01-05 1972-08-01 Motorola Inc Process for fabricating small geometry high frequency semiconductor device
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
US3793090A (en) * 1972-11-21 1974-02-19 Ibm Method for stabilizing fet devices having silicon gates and composite nitride-oxide gate dielectrics
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
US3886000A (en) * 1973-11-05 1975-05-27 Ibm Method for controlling dielectric isolation of a semiconductor device

Also Published As

Publication number Publication date
DE2626738C2 (de) 1982-05-27
JPS5346704B2 (it) 1978-12-15
FR2316733A1 (fr) 1977-01-28
GB1487547A (en) 1977-10-05
FR2316733B1 (it) 1979-07-27
CA1041227A (en) 1978-10-24
US3966514A (en) 1976-06-29
JPS525289A (en) 1977-01-14
DE2626738A1 (de) 1977-01-20

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