GB1527804A - Method of manufacturing integrated circuits - Google Patents
Method of manufacturing integrated circuitsInfo
- Publication number
- GB1527804A GB1527804A GB39502/76A GB3950276A GB1527804A GB 1527804 A GB1527804 A GB 1527804A GB 39502/76 A GB39502/76 A GB 39502/76A GB 3950276 A GB3950276 A GB 3950276A GB 1527804 A GB1527804 A GB 1527804A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- regions
- diodes
- sets
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/926—Elongated lead extending axially through another elongated lead
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
- Bipolar Transistors (AREA)
Abstract
1527804 Integrated circuits NCR CORP 23 Sept 1976 [1 Oct 1975] 39502/76 Heading H1K In a method of making an integrated circuit, in particular a diode matrix, two intersecting sets of parallel insulating regions are formed in a semi-conductor layer 14 provided in a substrate 12 of a conductivity type opposite to that of the layer, one of the sets extending only partially through the layer whereas the other extending completely through the layer such that interconnection between portions of the layer below the shallow insulating regions persists; and circuit components are formed in and/or on the isolated areas. Using photo-resist layers (18, 24), Figs. 1A, 3A (not shown), and a silicon nitride layer (16) as etching masks, the two sets of perpendicular grooves are formed in N-epitaxial silicon layer in two etching steps. The insulating material in the grooves is grown by oxidation of silicon in steam using silicon nitride as a mask, and this is followed by diffusion of boron from boron tribromide gas in the epitaxial layer to form diodes in the isolated areas. Metal contacts 42, Fig. 9A, in the diffused P-regions of the diodes are provided by sputter deposition through openings in an oxide passivating layer 30.1. P regions of the diodes in rows 1, 2, 3 are interconnected by conductive lead lines 42.1.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/618,717 US4032373A (en) | 1975-10-01 | 1975-10-01 | Method of manufacturing dielectrically isolated semiconductive device |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1527804A true GB1527804A (en) | 1978-10-11 |
Family
ID=24478852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB39502/76A Expired GB1527804A (en) | 1975-10-01 | 1976-09-23 | Method of manufacturing integrated circuits |
Country Status (8)
Country | Link |
---|---|
US (1) | US4032373A (en) |
JP (1) | JPS5244189A (en) |
CA (1) | CA1051123A (en) |
DE (1) | DE2643016A1 (en) |
FR (1) | FR2326779A1 (en) |
GB (1) | GB1527804A (en) |
IT (1) | IT1072436B (en) |
NL (1) | NL7610851A (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4139442A (en) | 1977-09-13 | 1979-02-13 | International Business Machines Corporation | Reactive ion etching method for producing deep dielectric isolation in silicon |
US4233671A (en) * | 1979-01-05 | 1980-11-11 | Stanford University | Read only memory and integrated circuit and method of programming by laser means |
US4394196A (en) * | 1980-07-16 | 1983-07-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of etching, refilling and etching dielectric grooves for isolating micron size device regions |
FR2491714A1 (en) * | 1980-10-06 | 1982-04-09 | Radiotechnique Compelec | SEMICONDUCTOR DEVICE WITH LOCALIZED ELECTROLUMINESCENT DIODES AND METHOD OF MANUFACTURING THE SAME |
US4491486A (en) * | 1981-09-17 | 1985-01-01 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing a semiconductor device |
JPS58105551A (en) * | 1981-11-20 | 1983-06-23 | Fujitsu Ltd | Semiconductor device |
JPS63101992A (en) * | 1986-10-17 | 1988-05-06 | 松下冷機株式会社 | Card encoder |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
JPH0547685A (en) * | 1991-08-07 | 1993-02-26 | Rohm Co Ltd | Method of diffusing impurity to semiconductor wafer |
US6448629B2 (en) * | 1999-07-29 | 2002-09-10 | International Business Machines Corporation | Semiconductor device and method of making same |
US7507440B2 (en) * | 2005-02-23 | 2009-03-24 | Ppg Industries Ohio, Inc. | Methods of forming composite coatings |
EP1804522A1 (en) | 2005-12-27 | 2007-07-04 | 3M Innovative Properties Company | A wire guide plate and a telecommunications module having a wire guide plate |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3005937A (en) * | 1958-08-21 | 1961-10-24 | Rca Corp | Semiconductor signal translating devices |
US3768150A (en) * | 1970-02-13 | 1973-10-30 | B Sloan | Integrated circuit process utilizing orientation dependent silicon etch |
US3796612A (en) * | 1971-08-05 | 1974-03-12 | Scient Micro Syst Inc | Semiconductor isolation method utilizing anisotropic etching and differential thermal oxidation |
US3928091A (en) * | 1971-09-27 | 1975-12-23 | Hitachi Ltd | Method for manufacturing a semiconductor device utilizing selective oxidation |
US3930300A (en) * | 1973-04-04 | 1976-01-06 | Harris Corporation | Junction field effect transistor |
FR2252638B1 (en) * | 1973-11-23 | 1978-08-04 | Commissariat Energie Atomique | |
US3892608A (en) * | 1974-02-28 | 1975-07-01 | Motorola Inc | Method for filling grooves and moats used on semiconductor devices |
-
1975
- 1975-10-01 US US05/618,717 patent/US4032373A/en not_active Expired - Lifetime
-
1976
- 1976-09-14 CA CA261,223A patent/CA1051123A/en not_active Expired
- 1976-09-23 GB GB39502/76A patent/GB1527804A/en not_active Expired
- 1976-09-24 DE DE19762643016 patent/DE2643016A1/en active Pending
- 1976-09-27 IT IT27686/76A patent/IT1072436B/en active
- 1976-09-29 FR FR7629215A patent/FR2326779A1/en active Granted
- 1976-09-30 JP JP51116703A patent/JPS5244189A/en active Granted
- 1976-09-30 NL NL7610851A patent/NL7610851A/en active Search and Examination
Also Published As
Publication number | Publication date |
---|---|
DE2643016A1 (en) | 1977-04-07 |
JPS5244189A (en) | 1977-04-06 |
FR2326779B1 (en) | 1980-12-12 |
JPH0145224B2 (en) | 1989-10-03 |
IT1072436B (en) | 1985-04-10 |
FR2326779A1 (en) | 1977-04-29 |
CA1051123A (en) | 1979-03-20 |
NL7610851A (en) | 1977-04-05 |
US4032373A (en) | 1977-06-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
746 | Register noted 'licences of right' (sect. 46/1977) | ||
PE20 | Patent expired after termination of 20 years |
Effective date: 19960922 |