DE2728318C2 - - Google Patents

Info

Publication number
DE2728318C2
DE2728318C2 DE2728318A DE2728318A DE2728318C2 DE 2728318 C2 DE2728318 C2 DE 2728318C2 DE 2728318 A DE2728318 A DE 2728318A DE 2728318 A DE2728318 A DE 2728318A DE 2728318 C2 DE2728318 C2 DE 2728318C2
Authority
DE
Germany
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2728318A
Other versions
DE2728318A1 (de
Inventor
Edward Baxter Purdy Station N.Y. Us Eichelberger
Eugen Igor Potomac Md. Us Muehldorf
Ronald Gene Vestal N.Y. Us Walther
Thomas Walter Longmont Col. Us Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2728318A1 publication Critical patent/DE2728318A1/de
Application granted granted Critical
Publication of DE2728318C2 publication Critical patent/DE2728318C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
DE19772728318 1976-06-30 1977-06-23 Verfahren zur pruefung der signalverzoegerung einer einseitig verzoegerungsabhaengigen, stufenempfindlichen einheit Granted DE2728318A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US05/701,054 US4074851A (en) 1976-06-30 1976-06-30 Method of level sensitive testing a functional logic system with embedded array
US05/701,041 US4063080A (en) 1976-06-30 1976-06-30 Method of propagation delay testing a level sensitive array logic system
US05/701,052 US4051352A (en) 1976-06-30 1976-06-30 Level sensitive embedded array logic system

Publications (2)

Publication Number Publication Date
DE2728318A1 DE2728318A1 (de) 1978-01-05
DE2728318C2 true DE2728318C2 (de) 1987-04-23

Family

ID=27418716

Family Applications (3)

Application Number Title Priority Date Filing Date
DE19772728318 Granted DE2728318A1 (de) 1976-06-30 1977-06-23 Verfahren zur pruefung der signalverzoegerung einer einseitig verzoegerungsabhaengigen, stufenempfindlichen einheit
DE2728676A Expired DE2728676C2 (de) 1976-06-30 1977-06-25 Stufenempfindliches, als monolithisch hochintegrierte Schaltung ausgeführtes System aus logischen Schaltungen mit darin eingebetteter Matrixanordnung
DE2729053A Expired DE2729053C2 (de) 1976-06-30 1977-06-28 Prüfverfahren für eine monolithisch integrierte stufenempfindliche, einseitig verzögerungsabhängige logische Einheit

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE2728676A Expired DE2728676C2 (de) 1976-06-30 1977-06-25 Stufenempfindliches, als monolithisch hochintegrierte Schaltung ausgeführtes System aus logischen Schaltungen mit darin eingebetteter Matrixanordnung
DE2729053A Expired DE2729053C2 (de) 1976-06-30 1977-06-28 Prüfverfahren für eine monolithisch integrierte stufenempfindliche, einseitig verzögerungsabhängige logische Einheit

Country Status (6)

Country Link
US (3) US4063080A (de)
JP (3) JPS533141A (de)
CA (3) CA1089031A (de)
DE (3) DE2728318A1 (de)
FR (1) FR2356997A1 (de)
GB (3) GB1581861A (de)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54121036A (en) * 1978-03-13 1979-09-19 Cho Lsi Gijutsu Kenkyu Kumiai Method of testing function of logic circuit
US4247817A (en) * 1978-05-15 1981-01-27 Teradyne, Inc. Transmitting electrical signals with a transmission time independent of distance between transmitter and receiver
FR2432175A1 (fr) * 1978-07-27 1980-02-22 Cii Honeywell Bull Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procede
DE2842750A1 (de) * 1978-09-30 1980-04-10 Ibm Deutschland Verfahren und anordnung zur pruefung von durch monolithisch integrierten halbleiterschaltungen dargestellten sequentiellen schaltungen
GB2030807B (en) * 1978-10-02 1982-11-10 Ibm Latch circuit
US4225957A (en) * 1978-10-16 1980-09-30 International Business Machines Corporation Testing macros embedded in LSI chips
US4244048A (en) * 1978-12-29 1981-01-06 International Business Machines Corporation Chip and wafer configuration and testing method for large-scale-integrated circuits
US4293919A (en) * 1979-08-13 1981-10-06 International Business Machines Corporation Level sensitive scan design (LSSD) system
US4320509A (en) * 1979-10-19 1982-03-16 Bell Telephone Laboratories, Incorporated LSI Circuit logic structure including data compression circuitry
DE2944149C2 (de) * 1979-11-02 1985-02-21 Philips Patentverwaltung Gmbh, 2000 Hamburg Integrierte Schaltungsanordnung in MOS-Technik
JPS5674759A (en) * 1979-11-26 1981-06-20 Hitachi Ltd Diagnostic system
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
JPS5737085U (de) * 1980-08-13 1982-02-26
JPS5789154A (en) * 1980-11-25 1982-06-03 Nec Corp Logical integrated circuit
US4392105A (en) * 1980-12-17 1983-07-05 International Business Machines Corp. Test circuit for delay measurements on a LSI chip
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4410987B1 (en) * 1981-07-13 1995-02-28 Texas Instruments Inc Preload test circuit for programmable logic arrays
US4517661A (en) * 1981-07-16 1985-05-14 International Business Machines Corporation Programmable chip tester having plural pin unit buffers which each store sufficient test data for independent operations by each pin unit
US4403287A (en) * 1981-08-24 1983-09-06 Bell Telephone Laboratories, Incorporated Microprocessor architecture having internal access means
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4477902A (en) * 1982-06-18 1984-10-16 Ibm Corporation Testing method for assuring AC performance of high performance random logic designs using low speed tester
US4489272A (en) * 1982-07-06 1984-12-18 International Business Machines Corporation Test circuit for turn-on and turn-off delay measurements
US4493077A (en) * 1982-09-09 1985-01-08 At&T Laboratories Scan testable integrated circuit
US4661922A (en) * 1982-12-08 1987-04-28 American Telephone And Telegraph Company Programmed logic array with two-level control timing
US4495629A (en) * 1983-01-25 1985-01-22 Storage Technology Partners CMOS scannable latch
US4791602A (en) * 1983-04-14 1988-12-13 Control Data Corporation Soft programmable logic array
US4564943A (en) * 1983-07-05 1986-01-14 International Business Machines System path stressing
US4580137A (en) * 1983-08-29 1986-04-01 International Business Machines Corporation LSSD-testable D-type edge-trigger-operable latch with overriding set/reset asynchronous control
US4554664A (en) * 1983-10-06 1985-11-19 Sperry Corporation Static memory cell with dynamic scan test latch
JPH07119790B2 (ja) * 1983-11-10 1995-12-20 株式会社日立製作所 半導体集積装置
CA1245244A (en) * 1984-04-30 1988-11-22 Richard S. Antoszewski Robotic wrist
JPS60254626A (ja) * 1984-05-30 1985-12-16 Sharp Corp ウエハテスト方法
JPH0772744B2 (ja) * 1984-09-04 1995-08-02 株式会社日立製作所 半導体集積回路装置
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
US5023775A (en) * 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US4684830A (en) * 1985-03-22 1987-08-04 Monolithic Memories, Inc. Output circuit for a programmable logic array
JPS61246844A (ja) * 1985-04-24 1986-11-04 Nec Corp バイボ−ラセミカスタムｌｓｉ
JPH0243680Y2 (de) * 1985-08-07 1990-11-20
US5032783A (en) * 1985-10-23 1991-07-16 Texas Instruments Incorporated Test circuit and scan tested logic device with isolated data lines during testing
US4710933A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Parallel/serial scan system for testing logic circuits
JPH0746120B2 (ja) * 1986-03-10 1995-05-17 株式会社東芝 テスト容易化回路及びテスト方法
US4726023A (en) * 1986-05-14 1988-02-16 International Business Machines Corporation Determination of testability of combined logic end memory by ignoring memory
KR910002236B1 (ko) * 1986-08-04 1991-04-08 미쓰비시 뎅기 가부시끼가이샤 반도체집적회로장치
KR900002770B1 (ko) * 1986-08-04 1990-04-30 미쓰비시 뎅끼 가부시끼가이샤 반도체 집적회로장치
JP2556017B2 (ja) * 1987-01-17 1996-11-20 日本電気株式会社 論理集積回路
US4764033A (en) * 1987-02-11 1988-08-16 Cincinnati Milacron, Inc. Oil film damper
US4876501A (en) * 1987-04-13 1989-10-24 Prime Computer, Inc. Method and apparatus for high accuracy measurment of VLSI components
US4780874A (en) * 1987-04-20 1988-10-25 Tandem Computers Incorporated Diagnostic apparatus for a data processing system
JPS649380A (en) * 1987-06-15 1989-01-12 Ibm Delay test for integrated circuit
JP2521774B2 (ja) * 1987-10-02 1996-08-07 株式会社日立製作所 メモリ内蔵型論理ｌｓｉ及びそのｌｓｉの試験方法
JPH01127049A (ja) * 1987-11-13 1989-05-19 Mitsubishi Atom Power Ind Inc 混合イオン交換樹脂の分離方法
JPH01163840A (ja) * 1987-12-21 1989-06-28 Nec Corp 遅延時間チエック方式
US5039939A (en) * 1988-12-29 1991-08-13 International Business Machines Corporation Calculating AC chip performance using the LSSD scan path
US5018144A (en) * 1989-04-28 1991-05-21 International Business Machines Corporation Logic performance verification and transition fault detection
US5023875A (en) * 1989-05-26 1991-06-11 Hughes Aircraft Company Interlaced scan fault detection system
JP2619957B2 (ja) * 1989-07-29 1997-06-11 富士通株式会社 ディレイテスト用クロック制御回路
US5274568A (en) * 1990-12-05 1993-12-28 Ncr Corporation Method of estimating logic cell delay time
US5291495A (en) * 1991-07-12 1994-03-01 Ncr Corporation Method for designing a scan path for a logic circuit and testing of the same
EP0531811B1 (de) * 1991-08-30 1997-04-23 Canon Kabushiki Kaisha Handgreifmechanismus für einen Roboter
US5331643A (en) * 1991-09-04 1994-07-19 International Business Machines Corporation Self-testing logic with embedded arrays
US5428713A (en) * 1991-11-25 1995-06-27 Kabushiki Kaisha Toshiba Compound module type manipulator apparatus
JPH05199080A (ja) * 1992-01-17 1993-08-06 Sony Corp 相補型論理回路
US5559715A (en) * 1992-03-11 1996-09-24 Vlsi Technology, Inc. Timing model and characterization system for logic simulation of integrated circuits which takes into account process, temperature and power supply variations
US5365528A (en) * 1992-04-03 1994-11-15 At&T Bell Laboratories Method for testing delay faults in non-scan sequential circuits
EP0596557B1 (de) * 1992-11-02 1999-03-03 Koninklijke Philips Electronics N.V. Optimale Entwurfmethode für synchrone digitale Schaltkreise durch Hertakten und selektives Setzen von Kipp-schaltungen
US5450418A (en) * 1992-12-23 1995-09-12 Advanced Micro Devices, Inc. Pseudo master slave capture mechanism for scan elements
US5696770A (en) * 1993-09-30 1997-12-09 Texas Instruments Incorporated Method and apparatus for testing circuitry with memory and with forcing circuitry
US5583787A (en) * 1994-03-08 1996-12-10 Motorola Inc. Method and data processing system for determining electrical circuit path delays
US5815512A (en) * 1994-05-26 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory testing device
US5499249A (en) * 1994-05-31 1996-03-12 At&T Corp. Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)
US5606567A (en) * 1994-10-21 1997-02-25 Lucent Technologies Inc. Delay testing of high-performance digital components by a slow-speed tester
US5732246A (en) * 1995-06-07 1998-03-24 International Business Machines Corporation Programmable array interconnect latch
US5684808A (en) * 1995-09-19 1997-11-04 Unisys Corporation System and method for satisfying mutually exclusive gating requirements in automatic test pattern generation systems
US5651013A (en) * 1995-11-14 1997-07-22 International Business Machines Corporation Programmable circuits for test and operation of programmable gate arrays
US6282506B1 (en) * 1996-02-20 2001-08-28 Matsushita Electric Industrial Co., Ltd. Method of designing semiconductor integrated circuit
US5787092A (en) * 1997-05-27 1998-07-28 Hewlett-Packard Co. Test chip circuit for on-chip timing characterization
US6898101B1 (en) 1997-12-16 2005-05-24 Cypress Semiconductor Corp. Microcontroller with programmable logic on a single chip
WO2001069390A2 (en) * 2000-03-15 2001-09-20 Arc Cores, Inc. Method and apparatus for debugging programs in a distributed environment
US6912601B1 (en) 2000-06-28 2005-06-28 Cypress Semiconductor Corp. Method of programming PLDs using a wireless link
US6640324B1 (en) * 2000-08-07 2003-10-28 Agere Systems Inc. Boundary scan chain routing
DE10144904C2 (de) * 2001-09-12 2003-08-21 Infineon Technologies Ag SIMD-Prozessor mit Unterprogramm-Steuereinheit
US8090564B1 (en) 2003-11-03 2012-01-03 Synopsys, Inc. Automatic generation of transaction level bus simulation instructions from bus protocol
US7451384B2 (en) * 2004-07-15 2008-11-11 Honeywell International Inc. Error recovery in asynchronous combinational logic circuits
US7716031B2 (en) * 2005-02-25 2010-05-11 Coware, Inc. Interface converter for unified view of multiple computer system simulations
US7742905B2 (en) * 2005-02-25 2010-06-22 Coware, Inc. Method and system for dynamically adjusting speed versus accuracy of computer platform simulation
US8543367B1 (en) 2006-02-16 2013-09-24 Synopsys, Inc. Simulation with dynamic run-time accuracy adjustment
US7899661B2 (en) 2006-02-16 2011-03-01 Synopsys, Inc. Run-time switching for simulation with dynamic run-time accuracy adjustment
US7884672B1 (en) 2006-11-01 2011-02-08 Cypress Semiconductor Corporation Operational amplifier and method for amplifying a signal with shared compensation components
US7779316B2 (en) * 2007-12-05 2010-08-17 Oracle America, Inc. Method of testing memory array at operational speed using scan
US7925937B2 (en) * 2008-01-07 2011-04-12 Advanced Micro Devices, Inc. Apparatus for testing embedded memory read paths
US10175942B2 (en) * 2014-02-19 2019-01-08 Ranganath Gururaj KULKARNI Elements of processor software

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3593317A (en) * 1969-12-30 1971-07-13 Ibm Partitioning logic operations in a generalized matrix system
US3633016A (en) * 1970-03-04 1972-01-04 Digital General Corp Apparatus and method for testing electrical systems having a plurality of terminals
US3659088A (en) * 1970-08-06 1972-04-25 Cogar Corp Method for indicating memory chip failure modes
US3714403A (en) * 1971-09-01 1973-01-30 Gte Automatic Electric Lab Inc Computer implemented method of detecting and isolating electrical faults in core memory systems
US3787817A (en) * 1972-06-21 1974-01-22 Us Navy Memory and logic module
US3784907A (en) * 1972-10-16 1974-01-08 Ibm Method of propagation delay testing a functional logic system
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3916306A (en) * 1973-09-06 1975-10-28 Ibm Method and apparatus for testing high circuit density devices
US3863232A (en) * 1973-12-26 1975-01-28 Ibm Associative array
US3983538A (en) * 1974-05-01 1976-09-28 International Business Machines Corporation Universal LSI array logic modules with integral storage array and variable autonomous sequencing
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals

Also Published As

Publication number Publication date
GB1581865A (en) 1980-12-31
CA1089031A (en) 1980-11-04
GB1581863A (en) 1980-12-31
JPS533754A (en) 1978-01-13
DE2728676C2 (de) 1982-04-29
GB1581861A (en) 1980-12-31
FR2356997A1 (fr) 1978-01-27
DE2728318A1 (de) 1978-01-05
US4063080A (en) 1977-12-13
US4074851A (en) 1978-02-21
FR2356997B1 (de) 1982-04-23
JPS533141A (en) 1978-01-12
US4051352A (en) 1977-09-27
JPS5539227B2 (de) 1980-10-09
DE2729053C2 (de) 1986-11-06
CA1075770A (en) 1980-04-15
CA1077567A (en) 1980-05-13
DE2728676A1 (de) 1978-01-12
DE2729053A1 (de) 1978-01-12
JPS533145A (en) 1978-01-12
JPS573107B2 (de) 1982-01-20

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Legal Events

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OD Request for examination
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee