DE3587715T2 - Integrierte Schaltung. - Google Patents

Integrierte Schaltung.

Info

Publication number
DE3587715T2
DE3587715T2 DE3587715T DE3587715T DE3587715T2 DE 3587715 T2 DE3587715 T2 DE 3587715T2 DE 3587715 T DE3587715 T DE 3587715T DE 3587715 T DE3587715 T DE 3587715T DE 3587715 T2 DE3587715 T2 DE 3587715T2
Authority
DE
Germany
Prior art keywords
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3587715T
Other languages
English (en)
Other versions
DE3587715D1 (de
Inventor
Shigeo Kuboki
Ikuro Masuda
Toshiaki Masuda
Terumine Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Publication of DE3587715D1 publication Critical patent/DE3587715D1/de
Application granted granted Critical
Publication of DE3587715T2 publication Critical patent/DE3587715T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
DE3587715T 1984-09-04 1985-08-27 Integrierte Schaltung. Expired - Fee Related DE3587715T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59185242A JPH0772744B2 (ja) 1984-09-04 1984-09-04 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE3587715D1 DE3587715D1 (de) 1994-02-17
DE3587715T2 true DE3587715T2 (de) 1994-08-04

Family

ID=16167372

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3587715T Expired - Fee Related DE3587715T2 (de) 1984-09-04 1985-08-27 Integrierte Schaltung.

Country Status (5)

Country Link
US (1) US4701922A (de)
EP (1) EP0173945B1 (de)
JP (1) JPH0772744B2 (de)
KR (1) KR900004888B1 (de)
DE (1) DE3587715T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106874177A (zh) * 2015-12-14 2017-06-20 中国航空工业第六八研究所 一种基于场景的锁存器测试方法

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US4931722A (en) * 1985-11-07 1990-06-05 Control Data Corporation Flexible imbedded test system for VLSI circuits
JPS6329276A (ja) * 1986-07-23 1988-02-06 Hitachi Ltd 論理ｌｓｉ
JPH0785099B2 (ja) * 1986-08-04 1995-09-13 三菱電機株式会社 半導体集積回路装置
KR910002236B1 (ko) * 1986-08-04 1991-04-08 미쓰비시 뎅기 가부시끼가이샤 반도체집적회로장치
KR900002770B1 (ko) * 1986-08-04 1990-04-30 미쓰비시 뎅끼 가부시끼가이샤 반도체 집적회로장치
US5451887A (en) * 1986-09-19 1995-09-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5365165A (en) * 1986-09-19 1994-11-15 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5367208A (en) 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
KR900008022B1 (ko) * 1986-10-16 1990-10-29 페어차일드 세미콘덕터 코퍼레이션 동기배열논리회로 및 시스템
JPS63256877A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp テスト回路
DE3719497A1 (de) * 1987-06-11 1988-12-29 Bosch Gmbh Robert System zur pruefung von digitalen schaltungen
US4862399A (en) * 1987-08-31 1989-08-29 General Electric Company Method for generating efficient testsets for a class of digital circuits
JPH01132979A (ja) * 1987-11-17 1989-05-25 Mitsubishi Electric Corp テスト機能付電子回路
JPH01132980A (ja) * 1987-11-17 1989-05-25 Mitsubishi Electric Corp テスト機能付電子回路装置
NL8800374A (nl) * 1988-02-16 1989-09-18 Philips Nv Geintegreerde monolithische schakeling met een testbus.
JPH0769396B2 (ja) * 1988-04-01 1995-07-31 日本電気株式会社 半導体集積回路装置
US4973904A (en) * 1988-12-12 1990-11-27 Ncr Corporation Test circuit and method
JP2612618B2 (ja) * 1989-10-13 1997-05-21 富士通株式会社 半導体集積回路装置
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
USRE36292E (en) * 1990-10-22 1999-09-07 Stmicroelectronics, Inc. Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit
IT1246301B (it) * 1990-10-22 1994-11-17 St Microelectronics Srl Dispositivo di analisi operativa di tipo scan path a singolo clock di scansione e singola fase di uscita per circuito integrato.
US5528600A (en) * 1991-01-28 1996-06-18 Actel Corporation Testability circuits for logic arrays
JP2817486B2 (ja) * 1991-11-29 1998-10-30 日本電気株式会社 論理集積回路
JPH05282890A (ja) * 1992-02-04 1993-10-29 Mitsubishi Electric Corp シフトレジスタ回路
JP3377225B2 (ja) * 1992-04-07 2003-02-17 富士写真フイルム株式会社 チェック回路を含む集積回路
JP2748069B2 (ja) * 1992-05-19 1998-05-06 三菱電機株式会社 フリップフロップ回路
US5495486A (en) * 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US6519724B1 (en) * 1999-03-22 2003-02-11 Koninklijke Philips Electronics N.V. Communication systems, circuits, circuit systems and methods of operating a circuit
KR100594257B1 (ko) * 2004-02-26 2006-06-30 삼성전자주식회사 내장형 셀프 테스트 회로를 가지는 ｓｏｃ 및 그 셀프테스트 방법
US7634749B1 (en) * 2005-04-01 2009-12-15 Cadence Design Systems, Inc. Skew insensitive clocking method and apparatus
US10605855B2 (en) * 2017-08-29 2020-03-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method, test line and system for detecting semiconductor wafer defects
US11567121B2 (en) * 2020-03-31 2023-01-31 Texas Instruments Incorporated Integrated circuit with embedded testing circuitry

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Publication number Priority date Publication date Assignee Title
US4034356A (en) * 1975-12-03 1977-07-05 Ibm Corporation Reconfigurable logic array
US4074851A (en) * 1976-06-30 1978-02-21 International Business Machines Corporation Method of level sensitive testing a functional logic system with embedded array
DE2842750A1 (de) * 1978-09-30 1980-04-10 Ibm Deutschland Verfahren und anordnung zur pruefung von durch monolithisch integrierten halbleiterschaltungen dargestellten sequentiellen schaltungen
JPS5674668A (en) * 1979-11-22 1981-06-20 Nec Corp Logical device
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4477902A (en) * 1982-06-18 1984-10-16 Ibm Corporation Testing method for assuring AC performance of high performance random logic designs using low speed tester
US4493077A (en) * 1982-09-09 1985-01-08 At&T Laboratories Scan testable integrated circuit
DE3274910D1 (en) * 1982-09-28 1987-02-05 Ibm Device for loading and reading different chains of bistable circuits in a data processing system
US4553236A (en) * 1983-01-25 1985-11-12 Storage Technology Partners System for detecting and correcting errors in a CMOS computer system
US4588944A (en) * 1983-06-13 1986-05-13 Sperry Corporation Fully scan-set testable embedded edge-triggered dual D and J-K flip-flops through testing as inverter strings

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106874177A (zh) * 2015-12-14 2017-06-20 中国航空工业第六八研究所 一种基于场景的锁存器测试方法

Also Published As

Publication number Publication date
DE3587715D1 (de) 1994-02-17
JPS6162878A (ja) 1986-03-31
EP0173945A2 (de) 1986-03-12
KR900004888B1 (ko) 1990-07-09
EP0173945A3 (en) 1988-07-20
JPH0772744B2 (ja) 1995-08-02
KR860002870A (ko) 1986-04-30
EP0173945B1 (de) 1994-01-05
US4701922A (en) 1987-10-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee