DE2554691C2 - Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung - Google Patents

Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung

Info

Publication number
DE2554691C2
DE2554691C2 DE2554691A DE2554691A DE2554691C2 DE 2554691 C2 DE2554691 C2 DE 2554691C2 DE 2554691 A DE2554691 A DE 2554691A DE 2554691 A DE2554691 A DE 2554691A DE 2554691 C2 DE2554691 C2 DE 2554691C2
Authority
DE
Germany
Prior art keywords
layer
copper
produced
titanium
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2554691A
Other languages
German (de)
English (en)
Other versions
DE2554691A1 (de
Inventor
William Francis Coplay Pa. Glick
Joseph Michael Bethlehem Pa. Morabito
John Henry Pickerington Ohio Thomas III
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/531,430 external-priority patent/US4068022A/en
Priority claimed from US05/576,711 external-priority patent/US4016050A/en
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE2554691A1 publication Critical patent/DE2554691A1/de
Application granted granted Critical
Publication of DE2554691C2 publication Critical patent/DE2554691C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/623—Porosity of the layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
    • H10W70/05—
    • H10W70/66—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrochemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electroplating Methods And Accessories (AREA)
DE2554691A 1974-12-10 1975-12-05 Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung Expired DE2554691C2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/531,430 US4068022A (en) 1974-12-10 1974-12-10 Methods of strengthening bonds
US05/576,711 US4016050A (en) 1975-05-12 1975-05-12 Conduction system for thin film and hybrid integrated circuits

Publications (2)

Publication Number Publication Date
DE2554691A1 DE2554691A1 (de) 1976-06-16
DE2554691C2 true DE2554691C2 (de) 1982-11-18

Family

ID=27063541

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2554691A Expired DE2554691C2 (de) 1974-12-10 1975-12-05 Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung

Country Status (8)

Country Link
JP (1) JPS6032311B2 (enExample)
DE (1) DE2554691C2 (enExample)
ES (1) ES443346A1 (enExample)
FR (1) FR2294610A1 (enExample)
GB (1) GB1527108A (enExample)
IT (1) IT1051461B (enExample)
NL (1) NL185249C (enExample)
SE (1) SE427400B (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4153518A (en) * 1977-11-18 1979-05-08 Tektronix, Inc. Method of making a metalized substrate having a thin film barrier layer
JPS54127572A (en) * 1978-03-28 1979-10-03 Oki Electric Ind Co Ltd Thin film circuit
DE2833919C2 (de) * 1978-08-02 1982-06-09 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von elektrischen Schichtschaltungen auf Kunststoffolien
JPS5559795A (en) * 1978-10-30 1980-05-06 Nippon Electric Co Printed circuit board and method of manufacturing same
DE2965814D1 (en) * 1979-03-21 1983-08-11 Bbc Brown Boveri & Cie Thin film resistor having a high temperature coefficient and method of manufacturing the same
FR2476913B1 (fr) * 1980-02-25 1985-09-13 Nippon Electric Co Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit
DE3029277C2 (de) * 1980-08-01 1983-10-20 Siemens AG, 1000 Berlin und 8000 München Aufbau von Metallschichten
DE3029382A1 (de) * 1980-08-01 1982-03-04 Siemens AG, 1000 Berlin und 8000 München Aufbau von metallschichten und verfahren zur herstellung dieses aufbaus
DE3107943A1 (de) * 1981-03-02 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von loetbaren und temperfaehigen edelmetallfreien duennschichtleiterbahnen
JPS57198696A (en) * 1981-06-01 1982-12-06 Shimada Rika Kogyo Kk Method of producing thin film circuit
DE3207659A1 (de) * 1982-03-03 1983-09-15 Siemens AG, 1000 Berlin und 8000 München Duennfilmschaltungen mit durchkontaktierungen
US4463059A (en) * 1982-06-30 1984-07-31 International Business Machines Corporation Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding
JPS59167096A (ja) * 1983-03-11 1984-09-20 日本電気株式会社 回路基板
JPS60140897A (ja) * 1983-12-28 1985-07-25 日本電気株式会社 樹脂絶縁多層基板
DE3433251A1 (de) * 1984-08-16 1986-02-27 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur herstellung von galvanischen lotschichten auf anorganischen substraten
US4808274A (en) * 1986-09-10 1989-02-28 Engelhard Corporation Metallized substrates and process for producing
EP0264648B1 (en) * 1986-09-25 1993-05-05 Kabushiki Kaisha Toshiba Method of producing a film carrier
JPH03108797A (ja) * 1989-09-22 1991-05-08 Ngk Spark Plug Co Ltd 多層配線基板およびその製造方法
DE4017181C2 (de) * 1990-05-29 1998-08-27 Daimler Benz Aerospace Ag Elektrisches Bauelement
WO1992015117A1 (fr) * 1991-02-25 1992-09-03 Sumitomo Electric Industries, Ltd. Tableau de connexions
US5449955A (en) * 1994-04-01 1995-09-12 At&T Corp. Film circuit metal system for use with bumped IC packages
DE10004453B4 (de) * 2000-02-03 2009-08-13 Ust Umweltsensortechnik Gmbh Elektrische Sicherung und Verfahren zu deren Herstellung
JP2003101222A (ja) * 2001-09-21 2003-04-04 Sony Corp 薄膜回路基板装置及びその製造方法
CN116093573A (zh) * 2022-12-14 2023-05-09 北京航天微电科技有限公司 一种微带电路制备方法以及微带环隔器

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2108730A1 (en) * 1970-03-06 1971-09-16 Motorola Inc Integrated hybrid circuit

Also Published As

Publication number Publication date
NL185249C (nl) 1990-02-16
NL185249B (nl) 1989-09-18
IT1051461B (it) 1981-04-21
JPS51101864A (en) 1976-09-08
GB1527108A (en) 1978-10-04
NL7514325A (nl) 1976-06-14
JPS6032311B2 (ja) 1985-07-27
SE427400B (sv) 1983-03-28
DE2554691A1 (de) 1976-06-16
ES443346A1 (es) 1977-08-16
FR2294610A1 (fr) 1976-07-09
SE7513853L (sv) 1976-06-11
FR2294610B1 (enExample) 1980-03-21

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Legal Events

Date Code Title Description
OD Request for examination
D2 Grant after examination