DE2062059A1 - Verfahren zur Herstellung von Tran si stören - Google Patents

Verfahren zur Herstellung von Tran si stören

Info

Publication number
DE2062059A1
DE2062059A1 DE19702062059 DE2062059A DE2062059A1 DE 2062059 A1 DE2062059 A1 DE 2062059A1 DE 19702062059 DE19702062059 DE 19702062059 DE 2062059 A DE2062059 A DE 2062059A DE 2062059 A1 DE2062059 A1 DE 2062059A1
Authority
DE
Germany
Prior art keywords
emitter
base layer
layer
zone
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702062059
Other languages
German (de)
English (en)
Inventor
Norbert William Iroma NJ Brackelmanns (VStA)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE2062059A1 publication Critical patent/DE2062059A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2608—Circuits therefor for testing bipolar transistors
    • G01R31/2614—Circuits therefor for testing bipolar transistors for measuring gain factor thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/162—Testing steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bipolar Transistors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Integrated Circuits (AREA)
DE19702062059 1969-12-17 1970-12-16 Verfahren zur Herstellung von Tran si stören Pending DE2062059A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88569969A 1969-12-17 1969-12-17

Publications (1)

Publication Number Publication Date
DE2062059A1 true DE2062059A1 (de) 1971-06-24

Family

ID=25387505

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702062059 Pending DE2062059A1 (de) 1969-12-17 1970-12-16 Verfahren zur Herstellung von Tran si stören

Country Status (7)

Country Link
US (1) US3666573A (https=)
JP (1) JPS4832938B1 (https=)
BE (1) BE760324A (https=)
DE (1) DE2062059A1 (https=)
FR (1) FR2068815B1 (https=)
GB (1) GB1281769A (https=)
SE (1) SE356848B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2949590A1 (de) * 1979-12-10 1981-06-11 Robert Bosch do Brasil, Campinas Verfahren zur vormessung von hochstromparametern bei leistungstransistoren und hierzu geeigneter leistungstransistor

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4046605A (en) * 1974-01-14 1977-09-06 National Semiconductor Corporation Method of electrically isolating individual semiconductor circuits in a wafer
FR2280203A1 (fr) * 1974-07-26 1976-02-20 Thomson Csf Procede d'ajustement de tension de seuil de transistors a effet de champ
DE3138340C2 (de) * 1981-09-26 1987-01-29 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum Herstellen von mehreren planaren Bauelementen
WO1999040170A1 (en) * 1998-02-04 1999-08-12 Unilever Plc Lavatory cleansing compositions
KR100663347B1 (ko) * 2004-12-21 2007-01-02 삼성전자주식회사 중첩도 측정마크를 갖는 반도체소자 및 그 형성방법
RU173641U1 (ru) * 2017-03-27 2017-09-04 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Тестовый планарный p-n-p транзистор

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL276676A (https=) * 1961-04-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2949590A1 (de) * 1979-12-10 1981-06-11 Robert Bosch do Brasil, Campinas Verfahren zur vormessung von hochstromparametern bei leistungstransistoren und hierzu geeigneter leistungstransistor

Also Published As

Publication number Publication date
FR2068815A1 (https=) 1971-09-03
BE760324A (fr) 1971-05-17
JPS4832938B1 (https=) 1973-10-09
FR2068815B1 (https=) 1976-04-16
GB1281769A (en) 1972-07-12
US3666573A (en) 1972-05-30
SE356848B (https=) 1973-06-04

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Legal Events

Date Code Title Description
OHW Rejection