BE760324A - Procede de fabrication de transistors, comprenant une etape de determination du gain - Google Patents

Procede de fabrication de transistors, comprenant une etape de determination du gain

Info

Publication number
BE760324A
BE760324A BE760324A BE760324A BE760324A BE 760324 A BE760324 A BE 760324A BE 760324 A BE760324 A BE 760324A BE 760324 A BE760324 A BE 760324A BE 760324 A BE760324 A BE 760324A
Authority
BE
Belgium
Prior art keywords
manufacturing process
determination step
transistor manufacturing
gain determination
gain
Prior art date
Application number
BE760324A
Other languages
English (en)
Inventor
N W Brackelmanns
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Publication of BE760324A publication Critical patent/BE760324A/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2608—Circuits therefor for testing bipolar transistors
    • G01R31/2614—Circuits therefor for testing bipolar transistors for measuring gain factor thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/162—Testing steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Integrated Circuits (AREA)
BE760324A 1969-12-17 1970-12-14 Procede de fabrication de transistors, comprenant une etape de determination du gain BE760324A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88569969A 1969-12-17 1969-12-17

Publications (1)

Publication Number Publication Date
BE760324A true BE760324A (fr) 1971-05-17

Family

ID=25387505

Family Applications (1)

Application Number Title Priority Date Filing Date
BE760324A BE760324A (fr) 1969-12-17 1970-12-14 Procede de fabrication de transistors, comprenant une etape de determination du gain

Country Status (7)

Country Link
US (1) US3666573A (fr)
JP (1) JPS4832938B1 (fr)
BE (1) BE760324A (fr)
DE (1) DE2062059A1 (fr)
FR (1) FR2068815B1 (fr)
GB (1) GB1281769A (fr)
SE (1) SE356848B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4046605A (en) * 1974-01-14 1977-09-06 National Semiconductor Corporation Method of electrically isolating individual semiconductor circuits in a wafer
FR2280203A1 (fr) * 1974-07-26 1976-02-20 Thomson Csf Procede d'ajustement de tension de seuil de transistors a effet de champ
DE2949590A1 (de) * 1979-12-10 1981-06-11 Robert Bosch do Brasil, Campinas Verfahren zur vormessung von hochstromparametern bei leistungstransistoren und hierzu geeigneter leistungstransistor
DE3138340A1 (de) * 1981-09-26 1983-04-14 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen von planaren bauelementen
ID26651A (id) * 1998-02-04 2001-01-25 Unilever Nv Komposisi pembersihan toilet
KR100663347B1 (ko) * 2004-12-21 2007-01-02 삼성전자주식회사 중첩도 측정마크를 갖는 반도체소자 및 그 형성방법
RU173641U1 (ru) * 2017-03-27 2017-09-04 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Тестовый планарный p-n-p транзистор

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL276676A (fr) * 1961-04-13

Also Published As

Publication number Publication date
US3666573A (en) 1972-05-30
GB1281769A (en) 1972-07-12
SE356848B (fr) 1973-06-04
JPS4832938B1 (fr) 1973-10-09
DE2062059A1 (de) 1971-06-24
FR2068815A1 (fr) 1971-09-03
FR2068815B1 (fr) 1976-04-16

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