DE112004001030B4 - FINFET mit Doppelsiliziumgateschicht für chemisch-mechanische Poliereinebnung - Google Patents

FINFET mit Doppelsiliziumgateschicht für chemisch-mechanische Poliereinebnung Download PDF

Info

Publication number
DE112004001030B4
DE112004001030B4 DE112004001030T DE112004001030T DE112004001030B4 DE 112004001030 B4 DE112004001030 B4 DE 112004001030B4 DE 112004001030 T DE112004001030 T DE 112004001030T DE 112004001030 T DE112004001030 T DE 112004001030T DE 112004001030 B4 DE112004001030 B4 DE 112004001030B4
Authority
DE
Germany
Prior art keywords
layer
semiconductor device
gate
gate structure
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE112004001030T
Other languages
German (de)
English (en)
Other versions
DE112004001030T5 (de
Inventor
Krishnashree San Ramon Achuthan
Shibly S. San Jose Ahmed
Haihong Milpitas Wang
Bin Cupertino Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE112004001030T5 publication Critical patent/DE112004001030T5/de
Application granted granted Critical
Publication of DE112004001030B4 publication Critical patent/DE112004001030B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0243—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE112004001030T 2003-06-12 2004-06-05 FINFET mit Doppelsiliziumgateschicht für chemisch-mechanische Poliereinebnung Expired - Fee Related DE112004001030B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/459,579 US6756643B1 (en) 2003-06-12 2003-06-12 Dual silicon layer for chemical mechanical polishing planarization
US10/459,579 2003-06-12
PCT/US2004/017725 WO2004112146A1 (en) 2003-06-12 2004-06-05 Finfet with dual silicon gate layer for chemical mechanical polishing planarization

Publications (2)

Publication Number Publication Date
DE112004001030T5 DE112004001030T5 (de) 2006-06-01
DE112004001030B4 true DE112004001030B4 (de) 2008-09-25

Family

ID=32508107

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112004001030T Expired - Fee Related DE112004001030B4 (de) 2003-06-12 2004-06-05 FINFET mit Doppelsiliziumgateschicht für chemisch-mechanische Poliereinebnung

Country Status (8)

Country Link
US (3) US6756643B1 (https=)
JP (1) JP2007500952A (https=)
KR (1) KR101123377B1 (https=)
CN (1) CN100477258C (https=)
DE (1) DE112004001030B4 (https=)
GB (1) GB2418534B (https=)
TW (1) TWI338328B (https=)
WO (1) WO2004112146A1 (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091068B1 (en) * 2002-12-06 2006-08-15 Advanced Micro Devices, Inc. Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization
US7087506B2 (en) * 2003-06-26 2006-08-08 International Business Machines Corporation Method of forming freestanding semiconductor layer
US7224029B2 (en) * 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
WO2005091374A1 (ja) * 2004-03-19 2005-09-29 Nec Corporation 半導体装置及びその製造方法
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7388257B2 (en) * 2004-09-01 2008-06-17 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
KR100678476B1 (ko) 2005-04-21 2007-02-02 삼성전자주식회사 씬 바디의 활성 영역 상에 적어도 두 개의 게이트 실리콘 패턴들을 갖는 더블 게이트 트랜지스터들 및 그 형성방법들
KR100657824B1 (ko) 2005-12-27 2006-12-14 주식회사 하이닉스반도체 핀 트랜지스터 및 그 제조 방법
CN101490822B (zh) * 2006-07-11 2011-03-16 Nxp股份有限公司 半导体器件及其制造方法
US8203182B2 (en) * 2007-03-14 2012-06-19 Nxp B.V. FinFET with two independent gates and method for fabricating the same
JP5371144B2 (ja) * 2007-06-29 2013-12-18 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の作製方法、並びに電子機器
US20090050975A1 (en) * 2007-08-21 2009-02-26 Andres Bryant Active Silicon Interconnect in Merged Finfet Process
US8497210B2 (en) 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
US8252689B2 (en) 2010-11-30 2012-08-28 Institute of Microelectronics, Chinese Academy of Sciences Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process
CN102479701B (zh) * 2010-11-30 2015-06-24 中国科学院微电子研究所 化学机械平坦化方法和后金属栅的制作方法
US20130189841A1 (en) * 2012-01-20 2013-07-25 Applied Materials, Inc. Engineering dielectric films for cmp stop
US9647066B2 (en) 2012-04-24 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy FinFET structure and method of making same
CN103426757B (zh) * 2012-05-15 2016-01-06 中芯国际集成电路制造(上海)有限公司 Ω形鳍式场效应晶体管的形成方法
CN103489780B (zh) * 2012-06-13 2016-02-17 中芯国际集成电路制造(上海)有限公司 鳍式场效应管基体的形成方法及鳍式场效应管
CN104008967B (zh) * 2013-02-25 2017-06-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9087796B2 (en) 2013-02-26 2015-07-21 International Business Machines Corporation Semiconductor fabrication method using stop layer
KR20150021811A (ko) * 2013-08-21 2015-03-03 삼성전자주식회사 반도체 소자의 제조방법
US20150200111A1 (en) * 2014-01-13 2015-07-16 Globalfoundries Inc. Planarization scheme for finfet gate height uniformity control
US9472572B2 (en) * 2014-05-06 2016-10-18 Globalfoundries Inc. Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins
CN105161418B (zh) * 2014-06-12 2019-04-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US9773871B2 (en) 2015-11-16 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
KR102647695B1 (ko) * 2016-08-12 2024-03-14 삼성디스플레이 주식회사 트랜지스터 표시판 및 그 제조 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010036731A1 (en) * 1999-12-09 2001-11-01 Muller K. Paul L. Process for making planarized silicon fin device
US20030057486A1 (en) * 2001-09-27 2003-03-27 International Business Machines Corporation Fin field effect transistor with self-aligned gate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260647A (ja) * 1993-03-04 1994-09-16 Sony Corp Ｘｍｏｓトランジスタの作製方法
JP2823819B2 (ja) * 1994-06-27 1998-11-11 松下電器産業株式会社 半導体装置およびその製造方法
JP3607431B2 (ja) * 1996-09-18 2005-01-05 株式会社東芝 半導体装置およびその製造方法
JP4389359B2 (ja) * 2000-06-23 2009-12-24 日本電気株式会社 薄膜トランジスタ及びその製造方法
FR2822293B1 (fr) * 2001-03-13 2007-03-23 Nat Inst Of Advanced Ind Scien Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6787439B2 (en) * 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010036731A1 (en) * 1999-12-09 2001-11-01 Muller K. Paul L. Process for making planarized silicon fin device
US20030057486A1 (en) * 2001-09-27 2003-03-27 International Business Machines Corporation Fin field effect transistor with self-aligned gate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Yang-Kyu Choi [u.a.]: Fin FET process refinements for improved mobility and Gate Workfunction Engineering. In: IEDM 2002, ISSN 0-7803-7462-2, S. 259-262 *

Also Published As

Publication number Publication date
JP2007500952A (ja) 2007-01-18
WO2004112146A1 (en) 2004-12-23
KR101123377B1 (ko) 2012-03-27
DE112004001030T5 (de) 2006-06-01
TWI338328B (en) 2011-03-01
TW200503095A (en) 2005-01-16
CN100477258C (zh) 2009-04-08
US6756643B1 (en) 2004-06-29
US20050056845A1 (en) 2005-03-17
US6982464B2 (en) 2006-01-03
US6812076B1 (en) 2004-11-02
CN1806340A (zh) 2006-07-19
GB2418534A (en) 2006-03-29
GB2418534B (en) 2007-01-31
KR20060013570A (ko) 2006-02-10
GB0524314D0 (en) 2006-01-04

Similar Documents

Publication Publication Date Title
DE112004001030B4 (de) FINFET mit Doppelsiliziumgateschicht für chemisch-mechanische Poliereinebnung
DE112004001041B4 (de) Verfahren zur Herstellung eines Halbleiterbauelements umfassend ein chemisch-mechanisches Mehrschrittpolierverfahren für einen Gatebereich in einem FINFET
DE112004000578B4 (de) Verfahren zur Herstellung eines Gates in einem FinFET-Bauelement und Dünnen eines Stegs in einem Kanalgebiet des FinFET-Bauelements
DE10393687B4 (de) Doppelgatehalbleiterbauelement mit separaten Gates und Verfahren zur Herstellung des Doppelgatehalbleiterbauelements
DE10393565B4 (de) Verfahren zur Herstellung eines Halbleiterelements mit einer U-förmigen Gate-Struktur
DE112006001735B4 (de) Blockkontaktarchitekturen für Transistoren mit Kanälen in einer Nano-Größenordnung und Verfahren zum Ausbilden
DE102008025708B4 (de) Kontaktstrukturen für FinFET-Bauelement und Verfahren zur Herstellung
DE112004000586B4 (de) Fin Fet-Bauelement und Verfahren zur Herstellung von Strukturen in Fin Fet-Bauelementen
DE102011015404B4 (de) Verfahren zur Herstellung eines FinFETs
DE102004042167B4 (de) Verfahren zum Ausbilden einer Halbleiterstruktur, die Transistorelemente mit unterschiedlich verspannten Kanalgebieten umfasst, und entsprechende Halbleiterstruktur
DE102017117942B4 (de) Herstellungsverfahren für eine Multi-Gate-Vorrichtung
DE112013001404B4 (de) Verfahren zum Verhindern eines Kurzschließens von benachbarten Einheiten
DE112004002633B4 (de) Verfahren zur Herstellung eines Steg-Feldeffekttransistors
DE102015110028A1 (de) Fin-Feldeffekttransistor(FinFET)-Bauelementstruktur
DE102019210597B4 (de) Verfahren zum Bilden von Abstandhaltern neben Gatestrukturen einer Transistorvorrichtung und integriertes Schaltungsprodukt
DE112005001488T5 (de) Tri-Gate Bauelement mit hoher Beweglichkeit und deren Herstellungsverfahren
DE112011105702T5 (de) Source-/Drain-Kontakte für nicht planare Transistoren
DE112004001442T5 (de) Variieren der Ladungsträgerbeweglichkeit in Halb-Leiterbauelementen, um Gesamtentwurfsziele zu erreichen
DE112004002107T5 (de) Selbstjustiertes Damaszener-Gate
DE102019214644B4 (de) Verfahren zu Herstellung einer Finfet-Struktur mit einem einen dielektrischen Streifen umfassenden Gate zur Reduzierung der effektiven Kapazität
DE102008059646A1 (de) Mehr-Gatetransistor mit Stegen mit einer Länge, die durch die Gateelektrode definiert ist
DE112004002640B4 (de) Verfahren zur Herstellung eines Stegfeldeffekttransistors, insb. eines Damaszener-Tri-Gate-FinFETs
DE102019121270B4 (de) Bildungsverfahren einer Halbleitervorrichtung mit Finnenstrukturen
EP1181723B1 (de) Doppel-gate-mosfet-transistor und verfahren zu seiner herstellung
DE102010046213B3 (de) Verfahren zur Herstellung eines Strukturelements und Halbleiterbauelement mit einem Strukturelement

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law

Ref document number: 112004001030

Country of ref document: DE

Date of ref document: 20060601

Kind code of ref document: P

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee