JP2007500952A - 化学機械研磨プレーナ化のためのデュアルシリコンゲート層を有するｆｉｎｆｅｔ - Google Patents

化学機械研磨プレーナ化のためのデュアルシリコンゲート層を有するｆｉｎｆｅｔ Download PDF

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Publication number
JP2007500952A
JP2007500952A JP2006533565A JP2006533565A JP2007500952A JP 2007500952 A JP2007500952 A JP 2007500952A JP 2006533565 A JP2006533565 A JP 2006533565A JP 2006533565 A JP2006533565 A JP 2006533565A JP 2007500952 A JP2007500952 A JP 2007500952A
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Japan
Prior art keywords
layer
semiconductor device
planarization
amorphous silicon
gate
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JP2006533565A
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Japanese (ja)
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JP2007500952A5 (https=
Inventor
アチュザン クリシュナシュリー
エス． アーメッド シブリー
ワン ハイホン
ユ ビン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2007500952A publication Critical patent/JP2007500952A/ja
Publication of JP2007500952A5 publication Critical patent/JP2007500952A5/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0243—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2006533565A 2003-06-12 2004-06-05 化学機械研磨プレーナ化のためのデュアルシリコンゲート層を有するｆｉｎｆｅｔ Ceased JP2007500952A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/459,579 US6756643B1 (en) 2003-06-12 2003-06-12 Dual silicon layer for chemical mechanical polishing planarization
PCT/US2004/017725 WO2004112146A1 (en) 2003-06-12 2004-06-05 Finfet with dual silicon gate layer for chemical mechanical polishing planarization

Publications (2)

Publication Number Publication Date
JP2007500952A true JP2007500952A (ja) 2007-01-18
JP2007500952A5 JP2007500952A5 (https=) 2009-05-21

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JP2006533565A Ceased JP2007500952A (ja) 2003-06-12 2004-06-05 化学機械研磨プレーナ化のためのデュアルシリコンゲート層を有するｆｉｎｆｅｔ

Country Status (8)

Country Link
US (3) US6756643B1 (https=)
JP (1) JP2007500952A (https=)
KR (1) KR101123377B1 (https=)
CN (1) CN100477258C (https=)
DE (1) DE112004001030B4 (https=)
GB (1) GB2418534B (https=)
TW (1) TWI338328B (https=)
WO (1) WO2004112146A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
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JP2007504679A (ja) * 2003-05-22 2007-03-01 フリースケール セミコンダクター インコーポレイテッド 個別ゲート構造を備えたトランジスタ
JP2009033134A (ja) * 2007-06-29 2009-02-12 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法、並びに電子機器

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US7091068B1 (en) * 2002-12-06 2006-08-15 Advanced Micro Devices, Inc. Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization
US7087506B2 (en) * 2003-06-26 2006-08-08 International Business Machines Corporation Method of forming freestanding semiconductor layer
US7224029B2 (en) * 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
WO2005091374A1 (ja) * 2004-03-19 2005-09-29 Nec Corporation 半導体装置及びその製造方法
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7388257B2 (en) * 2004-09-01 2008-06-17 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
KR100678476B1 (ko) 2005-04-21 2007-02-02 삼성전자주식회사 씬 바디의 활성 영역 상에 적어도 두 개의 게이트 실리콘 패턴들을 갖는 더블 게이트 트랜지스터들 및 그 형성방법들
KR100657824B1 (ko) 2005-12-27 2006-12-14 주식회사 하이닉스반도체 핀 트랜지스터 및 그 제조 방법
CN101490822B (zh) * 2006-07-11 2011-03-16 Nxp股份有限公司 半导体器件及其制造方法
US8203182B2 (en) * 2007-03-14 2012-06-19 Nxp B.V. FinFET with two independent gates and method for fabricating the same
US20090050975A1 (en) * 2007-08-21 2009-02-26 Andres Bryant Active Silicon Interconnect in Merged Finfet Process
US8497210B2 (en) 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
US8252689B2 (en) 2010-11-30 2012-08-28 Institute of Microelectronics, Chinese Academy of Sciences Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process
CN102479701B (zh) * 2010-11-30 2015-06-24 中国科学院微电子研究所 化学机械平坦化方法和后金属栅的制作方法
US20130189841A1 (en) * 2012-01-20 2013-07-25 Applied Materials, Inc. Engineering dielectric films for cmp stop
US9647066B2 (en) 2012-04-24 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy FinFET structure and method of making same
CN103426757B (zh) * 2012-05-15 2016-01-06 中芯国际集成电路制造(上海)有限公司 Ω形鳍式场效应晶体管的形成方法
CN103489780B (zh) * 2012-06-13 2016-02-17 中芯国际集成电路制造(上海)有限公司 鳍式场效应管基体的形成方法及鳍式场效应管
CN104008967B (zh) * 2013-02-25 2017-06-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9087796B2 (en) 2013-02-26 2015-07-21 International Business Machines Corporation Semiconductor fabrication method using stop layer
KR20150021811A (ko) * 2013-08-21 2015-03-03 삼성전자주식회사 반도체 소자의 제조방법
US20150200111A1 (en) * 2014-01-13 2015-07-16 Globalfoundries Inc. Planarization scheme for finfet gate height uniformity control
US9472572B2 (en) * 2014-05-06 2016-10-18 Globalfoundries Inc. Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins
CN105161418B (zh) * 2014-06-12 2019-04-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US9773871B2 (en) 2015-11-16 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
KR102647695B1 (ko) * 2016-08-12 2024-03-14 삼성디스플레이 주식회사 트랜지스터 표시판 및 그 제조 방법

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JPH06260647A (ja) * 1993-03-04 1994-09-16 Sony Corp Ｘｍｏｓトランジスタの作製方法
JPH0878684A (ja) * 1994-06-27 1996-03-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH1093093A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置およびその製造方法
JP2002009295A (ja) * 2000-06-23 2002-01-11 Nec Corp 薄膜トランジスタ及びその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005518094A (ja) * 2002-02-13 2005-06-16 フリースケール セミコンダクター インコーポレイテッド 縦型ダブルゲート半導体装置を形成する方法およびその構造
JP2006505950A (ja) * 2002-11-08 2006-02-16 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 分離した複数のゲートを有するダブルゲート半導体デバイス
JP2006505949A (ja) * 2002-11-08 2006-02-16 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 半導体デバイスのゲートのクリティカルディメンションを改善するためのゲート材料のプレーナ化

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US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
FR2822293B1 (fr) * 2001-03-13 2007-03-23 Nat Inst Of Advanced Ind Scien Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization

Patent Citations (8)

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Publication number Priority date Publication date Assignee Title
JPH06260647A (ja) * 1993-03-04 1994-09-16 Sony Corp Ｘｍｏｓトランジスタの作製方法
JPH0878684A (ja) * 1994-06-27 1996-03-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH1093093A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置およびその製造方法
JP2002009295A (ja) * 2000-06-23 2002-01-11 Nec Corp 薄膜トランジスタ及びその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005518094A (ja) * 2002-02-13 2005-06-16 フリースケール セミコンダクター インコーポレイテッド 縦型ダブルゲート半導体装置を形成する方法およびその構造
JP2006505950A (ja) * 2002-11-08 2006-02-16 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 分離した複数のゲートを有するダブルゲート半導体デバイス
JP2006505949A (ja) * 2002-11-08 2006-02-16 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 半導体デバイスのゲートのクリティカルディメンションを改善するためのゲート材料のプレーナ化

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007504679A (ja) * 2003-05-22 2007-03-01 フリースケール セミコンダクター インコーポレイテッド 個別ゲート構造を備えたトランジスタ
JP2009033134A (ja) * 2007-06-29 2009-02-12 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法、並びに電子機器

Also Published As

Publication number Publication date
WO2004112146A1 (en) 2004-12-23
KR101123377B1 (ko) 2012-03-27
DE112004001030T5 (de) 2006-06-01
TWI338328B (en) 2011-03-01
TW200503095A (en) 2005-01-16
CN100477258C (zh) 2009-04-08
DE112004001030B4 (de) 2008-09-25
US6756643B1 (en) 2004-06-29
US20050056845A1 (en) 2005-03-17
US6982464B2 (en) 2006-01-03
US6812076B1 (en) 2004-11-02
CN1806340A (zh) 2006-07-19
GB2418534A (en) 2006-03-29
GB2418534B (en) 2007-01-31
KR20060013570A (ko) 2006-02-10
GB0524314D0 (en) 2006-01-04

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