CN1806340A - 用于化学机械研磨平面化的双硅层鳍状场效应晶体管 - Google Patents

用于化学机械研磨平面化的双硅层鳍状场效应晶体管 Download PDF

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CN1806340A
CN1806340A CNA2004800161347A CN200480016134A CN1806340A CN 1806340 A CN1806340 A CN 1806340A CN A2004800161347 A CNA2004800161347 A CN A2004800161347A CN 200480016134 A CN200480016134 A CN 200480016134A CN 1806340 A CN1806340 A CN 1806340A
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semiconductor device
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amorphous silicon
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K·阿楚坦
S·S·艾哈迈德
汪海宏
俞斌
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Abstract

一种鳍状场效应晶体管型式的半导体装置，系包括有鳍结构(210)，于其上具有相对较薄的非晶硅层(420)而后再形成未掺杂的多晶硅层(425)。该半导体装置可使用化学机械研磨(CMP)将其平面化，其中该非晶硅层(420)系做为终止层(stop layer)以避免损害鳍结构。

Description

用于化学机械研磨平面化的双硅层鳍状场效应晶体管
技术领域
本发明有关于半导体装置及其制造方法。本发明对于双栅极装置(double gate devices)具有特别的适用性。
背景技术
由于对超大尺寸积体半导体装置相关的高密度及性能需求的逐渐提升，故须要求半导体装置的设计特征(design features)，如双栅极长度于100奈米(nm)以下、高可靠性以及提高制造产量。将设计特征缩小于100奈米以下将挑战传统方法的极限。
例如，当传统平面型金属氧化物半导体场效应晶体管(MOSFETs)的栅极长度在100奈米以下时，则与短沟道效应有关的问题，例如源极与漏级间的过量漏电流，将变得越来越难克服。此外，电子移动速度(mobility)的降低以及制造过程上的问题亦造成传统MOSFETs难以依比例缩小至包含逐渐减小的装置特征。因此将探究新的装置结构以改善FET性能并容许装置更进一步地缩小。
双栅极MOSFETs代表被视为可接替现存平面型MOSFETs的新结构的选择。在某些方面，双栅极MOSFETs较传统整块硅组件(bulksilicon)MOSFETs提供更佳特性。这些改善的产生系因为双栅极MOSFET于沟道的两侧均具有闸电极，而不似传统MOSFETs仅于单侧上具有闸电极。当存在两个闸电极时，通过漏级产生的电场可经由沟道的源极端行较佳遮蔽。此外，两个栅极可控制大约两倍于单栅极所控制的电流，因而导致较强的开关信号(switching signal)。
鳍状场效应晶体管(FinFET)系一种近来的双栅极结构，其显现良好的短沟道性能。FinFET包含一个形成于垂直鳍(vertical fin)内的沟道。FinFET结构系使用相似于传统平面型MOSFETs所用的布局(lay out)及制造过程技术所制造。
发明内容
与本发明一致的一实施例提供了一种双栅极MOSFET，其于栅极区上方具有双重多晶硅层以使用于提高多晶硅的化学机械研磨(chemical mechanical polishing，CMP)平面化。
与本发明一致的一实施例提供了一种制造半导体装置的方法。该方法包括于绝缘体上形成鳍结构并于至少一部份的鳍结构以及一部份的绝缘体的上方形成栅极结构。该栅极结构包括第一层以及形成于第一层上方的第二层。该方法进一步包括通过将栅极结构进行化学机械研磨(CMP)而将该栅极结构平面化。栅极结构第一层的平面化速率可能较栅极结构第二层的平面化速率慢。该平面化过程会持续直至第一层曝露于鳍结构上方的区域内。
与本发明一致的另一实施例系针对半导体装置。该装置包括形成于绝缘体上方的鳍结构。该鳍结构包括第一及第二端。于半导体装置中，至少一部份的鳍结构系做为沟道。将非晶硅层形成于至少一部份的鳍结构上方。多晶硅层则形成于至少一部份的非晶硅层周围。该非晶硅层突出通过鳍结构上方区域中的多晶硅层。源极区域连接于鳍结构的第一端。漏级区域连接于鳍结构的第二端。
附图说明
附图中，其中具有相同参考编号的组件于全文中表示相似组件。
图1表示范例半导体装置的横截面图；
图2A表示形成于图1所示的半导体装置上的鳍结构的腑视图；
图2B表示于图2A中沿着线A-A’的横截面图；
图3表示形成于图2B所示的鳍上的栅极介电层的横截面图；
图4表示沉积于图3所示的鳍上方的栅极材料层(gate materiallayers)的横截面图；
图5表示图4的栅极材料层于最初平面化后的横截面图；
图6表示图5的栅极材料层于进一步平面化后的横截面图；
图7概略表示FinFET的腑视图，其显现由图6所示的栅极材料为样本所绘得的栅极结构；
图8表示虚拟鳍(dummy fins)的横截面图；
图9是在概念上表示半导体装置上的线数组(an array of lines)，包括虚拟结构的图；
图10是在概念上表示半导体装置上另一个虚拟结构的图；以及图11至14图表示通孔(vias)形成的横截面图。
具体实施方式
本发明的下列详细叙述请参照附图。于不同图形中所使用的相同参考编号系用以定义相同或相似组件。此外，下列的详细叙述并不限制本发明。反之，本发明的领域范围系通过附加的申请专利范围及同等物所界定。
于此所使用的FinFET一词系指MOSFET的一种型式，其中，导电通路(conducting channel)系形成于垂直的硅“鳍”(fin)内。FinFETs为该技术领域所众所周知。
图1表示依据本发明的具体实施例所形成的半导体装置100的横截面图。参照图1，半导体装置100包括一种绝缘层上覆硅(silicon oninsulator，SOI)的结构，该结构包括硅基材110、埋藏氧化层120(buriedoxide layer)以及形成于埋藏氧化层120上方的硅层130。埋藏氧化层120及硅层130可经由传统方法形成于基材110上。
于一实施例中，埋藏氧化层120可包含二氧化硅且其厚度范围大约为1000至3000。硅层130可包含单晶或多晶硅。硅层130系使用于形成双栅极晶体管的鳍结构，以下将有更详尽的描述。
于另一个与本发明一致的实施例中，基材110与层130可包含其它半导体材料，如锗，或半导体材料的组合，如硅-锗。埋藏氧化层120亦可包含其它介电材料。
介电层140，例如氮化硅层或氧化硅层(例如，二氧化硅SiO2)，系形成于硅层130上方，以于随后的蚀刻过程期间做为保护罩。于一示范的实施例中，介电层140可长成的厚度范围大约为150至700。然后，光阻材料(photoresist material)可经沉积并经图案化以形成光阻光罩150(photoresist mask)而供随后制造过程使用。光阻可经由任何传统方法沉积并图案化(patterned)。
接着将半导体装置100蚀刻并移除光阻光罩150。于一示范的实施例中，硅层130可经由传统方法蚀刻并使蚀刻于埋藏氧化层120终止以形成鳍。于鳍形成后，可在邻近于鳍的各别端点形成源极和漏级区域。例如，于一示范的具体实施例中，可以传统方法沉积、图案化并蚀刻硅层、锗层或硅及锗的组合层以形成源极和漏级区域。于另一实施例中，可经由沉积及蚀刻硅层130以同时形成源极、漏级区域及鳍。
图2A图标说明以该方法所形成位于半导体装置100上的鳍结构的腑视图。根据本发明的示范具体实施例，于埋藏氧化层120上邻近于鳍结构210的端点可形成源极区域220及漏级区域230。
图2B系于图2A中沿着线A-A’的横截面图，该图标表示鳍结构210的形成。如上所述，可经由蚀刻介电层140及硅层130以形成包含具有介电覆层140(dielectric cap)的硅鳍130(silicon fin)的鳍结构210。
图3系依照本发明的示范具体实施例，说明鳍结构210上方的栅极介电层与门极材料的形成的横截面图。介电层可形成于硅鳍130的暴露侧表面上。例如，如图3所示，薄的氧化膜310可经热成长于鳍130上。该氧化薄膜310可长成大约50至100的厚度并形成于鳍130的暴露侧表面上。
在氧化薄膜310形成后，可将栅极材料层沉积于半导体装置100之上。参照图4，栅极材料层可包括非晶硅的薄层420以及于其后形成的未掺杂多晶硅层425。层420及425可通过使用传统化学气相沉积法(CVD)或其它习知技术而沉积。非晶硅层420可沉积至约为300的厚度。更明确地，非晶硅层420可沉积至厚度范围大约为200至600。多晶硅层425可沉积至厚度范围大约为200至1000。该厚度将可依据鳍或堆栈的高度而改变。
层420及425，尤其是层425，可于之后经平面化。与本发明的观点一致的，栅极材料层420及425可于平面化过程中利用非晶硅层420与多晶硅层425的不同研磨速率而经平面化。更具体地，其系通过利用非晶硅层420与多晶硅层425之间不同的研磨速率而控制非晶硅层420可保留于鳍210上的量。
CMP(Chemical Mechanical Polishing；化学机械研磨)为一种已知可使用于将半导体表面平面化的平面化技术。于CMP过程中，将晶圆表面朝下放置于旋转平台上。该晶圆以承载体适当地支承，并以相同于平台的方向旋转。平台的表面上系一研磨垫，于其上具有研磨液。该研磨液可包括在载体溶液(carrier solution)中具有氧化硅颗粒(silicaparticle)的胶体溶液。研磨液的化学组成及酸碱值(pH)会影响CMP程序的效能。于本发明的示范实施例中，系选择相较于多晶硅层，其对于非晶硅层具有低研磨速率的特定研磨液。使用于CMP的研磨液为该项技艺中所众所周知且通常为可购得的。许多商业上可购得且与研磨料例如氧化硅颗粒一起使用于氧化CMP的研磨液，系可经化学修饰而以不同速率研磨非晶硅及多晶硅层。研磨液可有7至12之间的不同的pH值。非晶硅层的移除速率可由50/min变化至2000/min，而非晶硅层的移除速率则可由500/min变化至6000/min。
图5系说明于最初时期的平面化完成后，栅极材料层420及425的平面化的横截面图。如图5所示，多晶硅层425经最初的平面化后，致使鳍210上的多晶硅层425的突出部位降低。图6图标说明经进一步CMP程序后的半导体装置100。此时，非晶硅层420的较高表面系暴露于鳍210上方的区域中。因为相较于多晶硅层425，CMP过程对于非晶硅层420具有相对较慢的研磨速率，故非晶硅层420可有效做为自动终止层(automatic stop layer)并继续存在做为鳍210上方的保护层。于CMP期间，小部份的非晶硅层420亦遭移除系可理解的。于此方法中，当栅极层420及425行平面化时，非晶硅层420可经使用以提供鳍210做为保护终止层(protective stopping layer)。非晶硅层420延伸至鳍210上方的最终厚度，如图6中的距离l1所示，例如，大约为300。
图7概略表示半导体装置100的腑视图，其说明经由栅极材料420及425图案化的栅极结构710。于CMP过程完成后，可将栅极结构710图案化并进行蚀刻。栅极结构710延伸穿过鳍210的沟道区域。栅极结构710可包括接近于鳍210的侧边的栅极部分以及由鳍210所区隔开的较大的电极部分。栅极结构710的电极部分可提供易使用的电接点(electrical contact)以加偏压(biasing)或者于其它方面控制该栅极部分。
而后再掺杂源极/漏级区域220与230。例如，将n-型式或p-型式的杂质(impurities)植入(implanted)源极/漏级区域220与230中。基于特定的最后完成装置(end device)需求，可选择特定的植入剂量及能量。熟悉此项技艺者即可有效完善地进行该以电路需求为基础的源极/漏级植入过程，因此为了避免不当混淆本发明的目标要旨，于此将不揭示该项行为。此外，侧壁间隔层(sidewall spacers)(未出示)可于源极/漏级离子植入前随意地形成以控制该以特定电路需求为基础的源极/漏级接合的位置。之后再执行活化退火(activation annealing)以活化源极/漏级区域220与230。
其它实施例
上述的CMP平面化过程可将栅极材料层平面化以形成半导体装置100的均匀表面。于某些实施例中，进一步改善平面化过程，此外，又将虚拟的鳍结构紧邻放置于鳍210旁以促进产生更加均匀的层。
图8系说明虚拟鳍(dummy fins)的横截面图。图8大致上相似于图4所示的横截面图，但是于图8中则形成了虚拟鳍801及802，紧邻于真实鳍810。虚拟鳍801及802于FinFET的最终运作中并未扮演角色。然而，通过将虚拟鳍801及802紧邻放置于鳍810旁，则当栅极材料层820于最初的沉积时即可形成较均匀的分布。亦即，虚拟鳍801及802可使鳍810的邻近区域中的层820的低处较不存在虚拟鳍801及802时更高。因此，于图8所示的实施例中，层820起始的沉积较不存在虚拟鳍801及802时更为均匀。故此可致使平面化后较佳的均匀性。
图9系于概念表示半导体装置上线数组(an array of lines)(例如，鳍)的图。线901表示实际上使用于FinFETs中的鳍。线902表示位于线901末端的虚拟鳍。虚拟鳍902可协助补偿由CMP过程所造成的侵蚀，因此可能产生较均匀的平面化表面。
图10系于概念表示另一个虚拟结构的实施例的图。线1001相似于线901，且表示使用于最终半导体装置中的真实结构。然而，虚拟线902则以结构1002取代。虚拟结构1002比虚拟线902包含更多区域且于平面化期间可提供较佳的均匀性。尤其，虚拟结构1002通过将线1001的图案封进内部，而可保护并阻止线1001的非均匀研磨。虚拟结构1002的尺寸，如长度l2，系依据使用于半导体装置上的总图案密度而定。
于包含CMP平面化过程的附加实施例中，参照第11至14图经叙述如下，CMP所导致的金属栅极积体层(metal gate integration layer)的不良影响将会减小。
当欲产生半导体逻辑(semiconductor logic)的垂直堆栈层时，则可于半导体装置中使用层间介电材料(ILD)层。如图11所示，可使用ILD层1101将第一半导体逻辑层1102与之后将于ILD层1101上方形成的第二半导体逻辑层分隔开。层1102并未详细显示于图11中，但可包含，例如，许多互连的(interconnected)FinFETs以执行一个或一个以上的逻辑功能。
通过抗蚀剂1104(resist)的应用将通孔(vias)1103图案化于ILD层1101。使用可容许层与层互相连接的导电材料将通孔1103填满(显示于第12至14图)。
参照图12，将通孔1103植入ILD 1101所环绕的区域中。植入材料(implantantion material)可包括硅(Si)或钯(Pd)，其可做为随后经沉积的金属的活化剂。亦可使用其它金属做为金属的无电电镀的活化剂。
参照第13及14图，将抗蚀剂1104移除后再将金属1406选择性地沉积。金属1406系通过选择的无电电镀法沉积，其可包括金属如钴(Co)、镍(Ni)或钨(W)或其合金。金属1406仅可沉积于以植入材料1205布植的区域上(即通孔1103经活化的表面)。因此，通孔1103系以导电材料填补。此步骤有助于避免CMP所导致的碟形凹陷(dishing)或其它不良影响。
于此描述了使用多栅极层(multiple gate layers)所产生的FinFET来改善平面化。多栅极层可包含一个薄的非晶硅层，其可于CMP步骤期间做为自动化的平面化终止层。
为了提供本发明的全盘了解，于先前叙述中已说明许多特定细节，例如特定的材料、结构、化学药品及步骤等。然而，本发明并不需要依靠在此所提出的特定细节即可实施。为了避免不必要地混淆本发明的目标要旨，于其它实施例中，则未详细描述习知的制造过程结构。
根据本发明，使用于制造半导体装置的介电层及导电层可通过传统的沉积技术沉积。例如，金属化技术，可使用如各种不同型式的化学气相沉积(CVD)步骤，包括低压化学气相沉积法(LPCVD)以及辅助化学气相沉积法(ECVD)。
本发明适用于半导体装置的制造且尤其适用于具有100奈米及100奈米以下的设计特征的半导体装置，其导致晶体管及电路速率的增加以及可靠度的改善。本发明适用于任何各种不同型式的半导体装置的形成，因此，为了避免混淆本发明的目标要旨，于此并未叙述其细节。于本发明的实行上，使用了传统的微影(photolithographic)及蚀刻技术，因此，在此并未详细描述该技术的细节。
于此揭示中，仅陈述本发明的较佳具体实施例及其某些多用途的范例。须了解本发明可使用于各种不同的其它组合及环境中，且可于本文所述发明概念的领域范围内进行修改。

Claims (10)

1.一种半导体装置的制造方法，包括：
于绝缘体上形成鳍结构(210)；
于至少一部份的鳍结构以及一部份的绝缘体的上方形成栅极结构，该栅极结构包含第一层(420)及形成于第一层上的第二层(425)；并且通过执行栅极结构的化学机械研磨(CMP)而将栅极结构平面化，该栅极结构第一层(420)的平面化速率比栅极结构第二层的平面化速率慢，该平面化过程会持续直至第一层的较高表面暴露于鳍上方的区域中。
2.如权利要求1所述的方法，其中该栅极结构的形成步骤包括：
沉积包含非晶硅的第一层(420)；以及
沉积包含未掺杂的多晶硅的第二层(425)。
3.如权利要求2所述的方法，其中该第一层沉积至厚度范围大约为200至800且该第二层沉积至厚度范围大约为200至1000。
4.如权利要求1所述的方法，其中该化学机械研磨包括使用研磨液将该栅极结构平面化，该方法进一步包括：
选择该研磨液使第一层的平面化速率约为2000/分钟而第二层的平面化速率约为50/分钟。
5.如权利要求1所述的方法，其中该半导体装置是鳍状场效应晶体管。
6.如权利要求1所述的方法，其中该平面化步骤系使用包含硅胶体研磨料且对氧化物具高选择性以及pH范围介于7至12之间的研磨液来进行。
7.一种半导体装置，包括形成于绝缘体(120)上方的鳍结构(210)，该鳍结构(210)包括第一及第二端，至少一部份的鳍结构系做为半导体装置中的沟道，该半导体装置包括：
形成于至少一部份的鳍结构上方的非晶硅层(420)；
形成由非晶硅层(420)部分所围绕的多晶硅层(425)，该非晶硅层(420)突出通过鳍结构上方区域中的多晶硅层；
连结至鳍结构的第一端的源极区域(220)；以及
连结至鳍结构的第二端的漏级区域(230)。
8.如权利要求7所述的半导体装置，其中该半导体装置是鳍状场效应晶体管。
9.如权利要求7所述的半导体装置，其中该位于鳍结构(210)上方区域中的非晶硅层(420)的厚度约为300。
10.如权利要求7所述的半导体装置，其中该非晶硅层(420)以及该多晶硅层(425)构成半导体装置的栅极材料层。
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WO2012071841A1 (zh) * 2010-11-30 2012-06-07 中国科学院微电子研究所 化学机械平坦化方法和后金属栅的制作方法
US8252689B2 (en) 2010-11-30 2012-08-28 Institute of Microelectronics, Chinese Academy of Sciences Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process
CN103426757A (zh) * 2012-05-15 2013-12-04 中芯国际集成电路制造(上海)有限公司 Ω形鳍式场效应晶体管的形成方法
CN103426757B (zh) * 2012-05-15 2016-01-06 中芯国际集成电路制造(上海)有限公司 Ω形鳍式场效应晶体管的形成方法
CN104008967B (zh) * 2013-02-25 2017-06-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN107731852A (zh) * 2016-08-12 2018-02-23 三星显示有限公司 晶体管显示面板及其制造方法
CN107731852B (zh) * 2016-08-12 2023-09-12 三星显示有限公司 晶体管显示面板及其制造方法

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US6982464B2 (en) 2006-01-03
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WO2004112146A1 (en) 2004-12-23
TWI338328B (en) 2011-03-01
KR101123377B1 (ko) 2012-03-27
US6756643B1 (en) 2004-06-29
DE112004001030B4 (de) 2008-09-25
TW200503095A (en) 2005-01-16
CN100477258C (zh) 2009-04-08
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US6812076B1 (en) 2004-11-02
US20050056845A1 (en) 2005-03-17
GB2418534B (en) 2007-01-31
GB2418534A (en) 2006-03-29

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