CN1921116A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN1921116A
CN1921116A CNA2006101083986A CN200610108398A CN1921116A CN 1921116 A CN1921116 A CN 1921116A CN A2006101083986 A CNA2006101083986 A CN A2006101083986A CN 200610108398 A CN200610108398 A CN 200610108398A CN 1921116 A CN1921116 A CN 1921116A
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semiconductor fin
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J·A·曼德尔曼
W·R·通蒂
R·A·小布思
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International Business Machines Corp
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Abstract

通过镶嵌方法在公共衬底上形成具有FinFET＝s和平面器件如MOSFET＝s的半导体结构的方法。利用镶嵌工艺在衬底上形成FinFET的半导体鳍片，其中鳍片生长被中断，以注入离子，随后所述注入的离子转变成将鳍片与衬底电隔离的区域。因为用于形成镶嵌－主体鳍片的掩模也用作注入离子的注入掩模，所以隔离区与鳍片自对准。在形成FinFET以及更具体地形成FinFET的栅极的处理过程中，所述鳍片可以由构图层支撑。通过使FinFET周围的衬底凹入和用介质材料至少部分地填充凹槽的自对准工艺也可以提供围绕FinFET的电隔离。

Description

半导体结构及其制造方法
技术领域
本发明总体上涉及半导体结构，以及更具体涉及在公共衬底上集成镶嵌-主体FinFET＝s和平面CMOS FET＝s的半导体结构以及制造这种半导体结构的方法。
背景技术
电路元件中的特征尺寸的逐渐小型化提高了性能和增加了集成电路的功能性能。鳍片型场效应晶体管(FinFETs)是可以被致密地封装在衬底上的低功率、高速晶体管。令人遗憾地，FinFET＝s不适合于集成电路设计中的所有目的。不同的应用需要不同的晶体管器件行为。在操作过程中，FinFET＝s被完全耗尽，这对于许多应用是合符需要的。但是，该电路设计也可能需要不到达完全耗尽的常规器件，如金属氧化物半导体场效应晶体管(MOSFET)。
通常，常规FinFET结构包括中心垂直半导体鳍片或主体，其包括中心沟道区，位于垂直鳍片的相对端、被中心沟道区分开的源极区和漏极区，以及覆盖沟道区的栅极导体。典型地，该半导体鳍片具有小于最小光刻尺寸的宽度和较高的纵横比。
在常规FinFET结构中，半导体鳍片是独立式的，以及在处理过程中不被周围的结构元件支撑。因此，在涉及例如超声波搅拌的工艺步骤过程中，易毁坏的和未被支撑的半导体鳍片具有断裂的显著风险。易毁坏的和未被支撑的半导体鳍片也可能被由激烈的温度变化而引起的热效应破裂，该激烈的温度变化是在形成FinFET的某些工序步骤过程中所经历的。
绝缘体上硅衬底公知包括FinFET＝s和平面MOSFET＝s，其中使用绝缘体上半导体(SOI)衬底的晶体硅作为籽晶层，通过沟槽形成FinFET的半导体鳍片。但是，因为隔离问题，这些常规制造技术专有地应用于SOI衬底，其中SOI层的晶体硅通过掩埋绝缘体层与衬底的下面部分电隔离。因此，这些常规制造技术不适用于在公共体衬底上集成FinFET＝s和平面器件如MOSFET＝s。
因此需要一种包括镶嵌-主体FinFET＝s和平面MOSFET＝s的体衬底，以及用于在公共体衬底或SOI衬底上形成镶嵌-主体FinFET＝s和平面MOSFET＝s的制造方法，其克服常规衬底以及制造这种衬底的常规方法的这些及其它缺点。
发明内容
本发明总体涉及在公共衬底上集成镶嵌-主体FinFET＝s和平面CMOSFET＝s。根据本发明的一个方面，一种半导体结构包括单晶的体衬底、在单晶的体衬底中形成的多个平面器件和多个鳍片型场效应晶体管。每个鳍片型场效应晶体管与单晶的体衬底电隔离以及也与平面器件电隔离。
在本发明的另一方面中，一种制造半导体结构的方法包括：在掩模中蚀刻沟槽，以及在沟槽中形成半导体鳍片。该方法还包括在形成与半导体鳍片的沟道区交叉的栅极结构的同时，用掩模支撑半导体鳍片。
在本发明的另一方面中，一种制造半导体结构的方法包括：在覆盖衬底的掩模中蚀刻沟槽，在沟槽中形成第一外延层，以及穿过掩模将离子注入第一外延层中，以便沟槽将注入的离子与第一外延层自对准。该方法还包括将注入的离子转变为将第一外延层与衬底电隔离的掩埋隔离区，然后在沟槽中和第一外延层上形成第二外延层。
在本发明的又一方面中，一种制造半导体结构的方法包括：形成从衬底凸出的半导体鳍片，以及蚀刻围绕半导体鳍片的衬底的部分，以在半导体鳍片的基底(base)周围的衬底中限定凹槽。该方法还包括至少部分地用介质材料填充凹槽，以使半导体鳍片与衬底电隔离。
附图说明
引入并构成说明书的一部分的附图与上面给出的本发明的概述和如下给出的实施例的详细描述一起说明本发明的实施例和用来解释本发明的原理。
图1-14是根据本发明的实施例，在处理方法的各个制造阶段的部分衬底的示意图，其中A表示顶视图，B是通常沿A中的线B-B的相应剖面图；以及
图15-20是根据本发明的另一选择性实施例，在处理方法的各个制造阶段的部分衬底的示意性剖面图，其中A表示顶视图，B是通常沿A中的线B-B的相应剖面图。
具体实施方式
现在将通过参考伴随本申请的附图更详细地描述本发明，本发明提供一种在公共体衬底或在绝缘体上硅(SOI)衬底上集成鳍片型场效应晶体管(FinFET＝s)和平面互补金属氧化物半导体(CMOS)器件，如场效应晶体管(FET＝s)的半导体结构，以及用于制造这些结构的方法。
图1-14图示了本发明的一个实施例中采用的制造阶段。在这些图中，标有“A”的视图是在一个制造阶段的半导体结构的顶视图，而标有“B”的视图是该半导体结构的剖面图。
参考图1A，B，根据本发明的一个实施例的初始制造阶段，提供或获得单晶衬底10。衬底10可以是任意类型的常规单晶半导体衬底，如所示的体硅衬底或例如绝缘体上半导体(SOI)衬底的有源层。在衬底10的露出表面15上形成氧化物(SiOx)的较厚衬垫氧化物层12。衬垫氧化物层12可以通过常规热化学气相淀积(CVD)工艺来淀积或通过常规湿法或干法热氧化工艺来生长。衬垫氧化物层12将随后部分地产生用于半导体鳍片30的隔离(图6A，B)以及也将减小寄生栅极电容。优选，衬垫氧化物层12的垂直厚度约为50纳米(nm)至约200nm。
在衬垫氧化物层12上形成衬垫氮化物层14。衬垫氮化物层14由利用常规淀积工艺如CVD或等离子体辅助CVD形成的氮化硅(Si3N4)构成。衬垫氮化物层14的硬度和耐磨性足以在后续制造阶段过程中用作硬掩模和用作抛光停止层。形成衬垫氮化物层14的材料也必须对衬垫氧化物层12具有蚀刻选择性。衬垫氮化物层14的垂直厚度优选约50nm至约500nm，该垂直厚度将决定鳍片高度。
参考图2A，B，其中相同的参考标号指图1A，B中和后续制造阶段中的相同特征，通过常规光刻和蚀刻方法，在衬垫氧化物层12和衬垫氮化物层14中形成构图的开口或沟槽16。沟槽16从基本上平坦的表面26垂直地延伸至衬底10的深度，该平坦的表面26在该制造阶段被定义为衬垫氮化物层14的上水平表面。应当注意尽管该图图示了一个沟槽16的形成，但是本发明预期在该半导体结构中形成多个这种沟槽16。每个沟槽16最终限定之后的制造阶段的一个FinFET 72(图14A，B)的鳍片30(图6A，B)和源极和漏极区32，34(图6A，B)。
通过任意常规光刻技术形成沟槽16的图形，每个沟槽16的图形典型地是H形，所述光刻技术包括横穿衬垫氮化物层14的表面施加抗蚀剂(未示出)，将抗蚀剂暴露于辐射图形，以及在曝光的光致抗蚀剂中显影转移的图形。适合的光刻技术包括具有或者没有相移的光刻、X射线光刻、电子束光刻、或形成用于鳍片30的沟槽16的一部分的侧壁图像转移技术和形成用于限定FinFET 72(图14A，B)的源极-漏极区32，34的沟槽16的另一部分的常规光刻的组合。
对构成衬垫氧化物层12的材料具有选择性的常规各向异性干法蚀刻工艺，如反应离子蚀刻(RIE)或等离子体蚀刻用来将沟槽图形转移到衬垫氮化物层14中至衬垫氧化物层12的深度。可以用一个蚀刻步骤或多个步骤进行的蚀刻工艺的化学反应除去通过沟槽图形可见的部分衬垫氮化物层14以及垂直地停止在衬垫氧化物层12上。通过对构成衬底10的材料具有选择性的其它常规各向异性干法蚀刻工艺如RIE或等离子蚀刻，沟槽图形被延伸至衬底10的深度。可以用一个蚀刻步骤或多个步骤进行的蚀刻工艺的化学反应除去通过构图的衬垫氮化物层14可见的部分衬垫氧化物层12并垂直地停止在衬底10上。
参考图3A，B，其中相同的参考标号指图2A，B中以及在后续制造阶段中的相同特征，在每个沟槽16内有选择地形成适合的半导体材料如硅的外延层18。外延层18未完全填充每个沟槽16，而是垂直地延伸，以仅仅部分地填充每个沟槽16。优选，外延层18的垂直高度约在25nm和约100nm之间。在每个沟槽16的基底处的衬底10的露出表面作为晶体生长的籽晶以及通过提供用于生长外延层18的材料的模板决定外延层18的晶体取向，其中该模板被复制。形成外延层18的半导体材料优选在外延层18的垂直高度上，在围绕每个沟槽16的衬垫氧化物层12和衬垫氮化物层14的垂直表面上不形成有明显的厚度。在衬底10和外延层18之间提供电绝缘之后，在后续制造阶段随后再继续外延层18的生长，如下所述。
适合于形成外延层18的一种工艺是在亚大气工艺压力下执行和具有约850EC和约1050EC之间的衬底温度的选择性外延生长(SEG)工艺。典型的工艺条件约为40乇和约900EC。对于SEG工艺，优选的硅源包括但是不局限于四氯化硅(SiCl4)、三氯硅烷(SiHCl3)和二氯硅烷(SiH2Cl2)。在硅源中氯气的存在增加围绕每个沟槽16和外延层18的垂直高度上的衬垫氧化物层12和衬垫氮化物层14的区域上的生长限制的选择性。该选择性生长保持外延层18中的材料的晶体结构，而不引入对FinFET 72(图14A，B)的操作有害的显著晶格缺陷。
参考图4A，B，其中相同的参考标号指图3A，B中和后续制造阶段的相同特征，用含氧离子20，如原子或分子氧离子，以近似地垂直的入射离子注入外延层18。对于在离子范围周围垂直地分布的所得氧浓度分布22，离子的注入能量导致较浅的深度。氧浓度分布22的最终峰值浓度近似地位于衬底10和外延层18之间的界面处并与衬垫氧化物层12重叠。例如，可以在约25keV至100keV范围内的能量下以及在约2×1017cm-2至约5×1018cm-2的离子剂量范围下注入O+种类的离子20。在随后的制造阶段，氧浓度分布22转变成位于鳍片30下面并将半导体鳍片30(图6A，B)与衬底10隔离的掩埋隔离区24(图5A，B)。本发明预期除氧之外或代替氧的其它离子种类可以被注入，以为半导体鳍片30提供需要的电隔离。
通过衬垫氧化物层12和衬垫氮化物层14中的沟槽16注入含氧离子20，相对于鳍片30自对准掩埋隔离区24。每个开口沟槽16的侧壁17用来掩蔽衬底10，基本上限定隔离区24的横向范围。尽管离子20近似垂直入射撞击外延层18，但是高能离子20的横向漫延使得浓度分布22横向地延伸到垂直凸出的侧壁17到衬底10中和到衬垫氧化物层12中，因此在垂直于离子入射方向的方向中。
有利地，在层18的形成停止之后，通过较薄的外延层18以低注入能量注入含氧离子20，限制了氧浓度分布22在外延层18中的垂直离子漫延。如果外延层18完全填充每个沟槽16，需要显著地更高的注入能量，这将增加由外延层18产生的晶格损伤，以及因为增加的垂直离子漫延，使之更难以控制氧浓度分布22的最终深度。在离子20的注入之后，在氧浓度分布22上的部分外延层18基本上不被损伤，因此在后续工序步骤中可以用作籽晶层，以继续层18的外延生长，如下所述。
参考图5A，B，其中相同的参考标号指图4A，B中和后续制造阶段的相同特征，在适合的气氛，如惰性气体气氛或真空中，热处理或退火外延层18，以除去由离子20的注入产生的外延层18的离子产生损伤。该退火可以在约1100EC和约1300EC之间的衬底温度下执行，通过使由在外延层18和衬底10中的浓度分布22限定的富氧材料接合并限定隔离区24，完全地形成掩埋隔离区24。
参考图6A，B，其中相同的参考标号指图5A，B中和后续制造阶段的相同特征，退火之后再继续外延层18的选择性形成。该再继续形成可以使用，例如SEG，来淀积构成外延层18的材料的附加厚度。外延层18的最初形成部分用作用于再继续形成的籽晶，以便通过提供用于新增加材料的生长模板，初始结晶性继续存在于新增加的材料中，其中该模板被复制。外延层18形成至在衬垫氮化物层14的顶部水平表面上凸出的垂直高度。然后通过平面化工艺，如化学机械抛光(CMP)工艺，使得外延层18的上水平表面与衬垫氮化物层14的上水平表面基本上共面，以重建基本上平坦的表面26和完成镶嵌工艺。这种常规CMP平面化工艺结合研磨和溶解，以除去残留在衬垫氮化物层14上的过量的外延层18的过剩材料，以及垂直地停止在衬垫氮化物层14上。
该平坦的外延层18相对于平面表面26凹入至约10nm至100nm的深度，例如通过各向异性干法蚀刻工艺。然后在平面表面26上形成绝缘体的覆盖层，如CVD氧化物。平面表面26的基本平面性通过平面化工艺如CMP平面化工艺来重建，其除去过量的覆盖绝缘体层，以及停止在衬垫氮化物层14的上水平表面的垂直水平处。绝缘体层的剩余部分填充外延层18的每个凹槽部分上的空间，因此在形成外延层18的材料上限定保护绝缘覆层28。
每个沟槽16中的外延层18限定薄的中心半导体主体或鳍片30以及源极和漏极区32，34，其被认为是包括鳍片30的两端的扩大接触。鳍片30从与衬底10的界面垂直地凸出以及被衬垫氧化物层12的材料和构成衬垫氮化物层14的材料横向地支撑。
参考图7A，B，其中相同的参考标号指图6A，B中和后续制造阶段的相同特征，通过常规光刻和蚀刻方法，在横穿衬底10的各个位置形成浅沟槽隔离(STI)区36，该方法涉及掩蔽平面表面26和通过衬垫氧化物层12和衬垫氮化物层14利用RIE或等离子体蚀刻来蚀刻沟槽(在图7A，B中显示为被填充)，以及使浅深度继续到衬底10中。在蚀刻到衬底10中之后，可选的里衬(未示出)可以应用于沟槽。淀积适合于形成STI区36的绝缘体的覆盖层，如CVD氧化物如TEOS或HDP氧化物，其部分填充沟槽。通过常规平面化工艺，如化学机械抛光(CMP)工艺，重建平面表面26的基本平面性，其除去过量的覆盖绝缘体层并停止在衬垫氮化物层14的上水平表面上。
参考图8A，B，其中相同的参考标号指图7A，B中和后续制造阶段的相同特征，阻挡掩模38被应用于平面表面26，以覆盖和保护外延层18和围绕外延层18的部分硬掩模层。使用连续的各向异性干法蚀刻工艺，以除去未被阻挡掩模38保护的部分衬垫氧化物层12和衬垫氮化物层14，以限定通向衬底10的凹槽区40，用于平面器件的后续制造。第一各向异性干法蚀刻工艺对衬垫氧化物层12的材料具有选择性地除去衬垫氮化物层14的材料。第二各向异性干法蚀刻工艺对衬垫氮化物层14的材料具有选择性地除去衬垫氧化物层12的材料。阻挡掩模38不需要重叠STI区36，但是必须覆盖用于FinFET＝s 72(图14A，B)的后续形成的指定区域以避免蚀刻绝缘覆层28。在凹槽区40被限定之后，阻挡掩模38被剥离，以露出平面表面26，其平面性现在被凹槽区40的存在而中断。
参考图9A，B，其中相同的参考标号指图8A，B中和后续制造阶段中的相同特征，在每个凹槽区40中通过本领域的普通技术人员所理解的一系列常规处理步骤形成平面半导体器件，该半导体器件通常由参考标号42表示，以及为了论述被图示为金属氧化物半导体场效应晶体管(MOSFET)。器件42包括通过薄的栅极介质46与衬底10隔开的栅极电极44。栅极电极44可以是掺杂以高度导电的多晶硅(Apolysilicon≌)或可以由一种或多种金属形成，如钼、钛、钽或镍、金属硅化物或金属氮化物。栅极介质46可以包括由干氧环境或蒸汽生长的氧化物(即，SiO2)或其它材料如Si3N4、氮氧化物(SiOxNy)、SiO2和Si3N4的栅极介质叠层或金属氧化物如Ta2O5。
由材料如Si3N4在栅极电极44的侧壁上及其它露出的垂直表面上形成侧壁隔离物48。栅极电极44和/或侧壁隔离物48可以用作自对准的掩模，用于形成源极区50和漏极区52的一种或多种离子注入。用于注入掺杂剂以形成源极和漏极区50，52的技术是本领域普通技术人员所熟知的。另外，可以通过掺杂剂扩散或掺杂剂扩散和离子注入的结合形成源极和漏极区50，52。位于源极和漏极区50，52之间的衬底10的部分包括沟道54，该沟道具有由从电源提供给栅极电极44的电压控制的电阻率，栅极电极44通过栅极介质46与沟道54静电耦合。最终，淀积绝缘体层56，其优选是可软回流的和容易平面化的氧化物，如硼磷硅玻璃(BPSG)、硼硅玻璃(BSG)、磷硅玻璃(PSG)或未密化的原硅酸四乙酯(TEOS)，以填充每个凹槽区40的剩余开口空间。通过常规平面化工艺如CMP平面化绝缘体层56，以对衬垫氮化物层14的水平表面重建平面表面26的基本平面性。
参考图10A，B，其中相同的参考标号指图9A，B中和后续制造阶段的相同特征，通过常规光刻和蚀刻工艺在衬垫氮化物层14中形成栅极沟槽58，其中通过例如对氧化物层12的材料具有选择性的RIE或等离子体蚀刻，除去通过可移走保护掩模(未示出)中的构图开口露出的衬垫氮化物层14的区域。每个栅极沟槽58延伸至氧化物层12的垂直水平。接着栅极沟槽58被部分导体填充，以提供用于每个FinFET 72(图14A，B)的一组栅极68，69。穿过外延层18的构成半导体材料的沟道区64，半导体鳍片30的相对垂直侧壁60，62被露出。源极和漏极区32，34保持被衬垫氮化物层14覆盖和保护。除沿垂直侧壁60，62露出的鳍片30的长度部分以外，半导体鳍片30的剩余部分保持被衬垫氧化物层12和衬垫氮化物层14支撑。
可以通过例如气相掺杂剂扩散工艺或倾斜离子注入，选择性地掺杂沟道区64。沟道区64的可选沟道掺杂典型地将需要使用多个掩模(未示出)，如光致抗蚀剂掩模，以在各个水平中引入不同的掺杂剂，以形成各种阈值电压的N沟道FinFET＝s和P沟道FinFET＝s。如果沟道区64中的鳍片30的厚度足够地窄，那么沟道掺杂可以省略，因为在FinFET 72(图14A，B)的工作过程中，沟道区64中的本征半导体材料被完全地耗尽。
参考图11A，B，其中相同的参考标号指图10A，B中和后续制造阶段的相同特征，在每个半导体鳍片30的沟道区64的露出相对侧壁60，62上形成栅极介质66。栅极介质66可以由任意常规栅极绝缘体材料构成，包括但不限于氧化硅(SiOx)、氮氧化硅(SiOxNy)、氮化硅(Si3N4)、高介电常数(高-K)介质如硅铪氮氧化物或其组合，如所属领域的普通技术人员所公知的。栅极介质66的厚度优选在约1nm至约6nm的范围内。
参考图12A，B，其中相同的参考标号指图11A，B中和后续制造阶段的相同特征，通过淀积栅极导体以填充每个栅极沟槽58，然后使用在衬垫氮化物层14上停止的常规平面化工艺如CMP平面化淀积的栅极导体以重建平面表面26的基本平面性，形成FinFET 72(图14A，B)的栅极68，69。所属领域的普通技术人员理解这种工艺是镶嵌工艺。栅极68，69的导体可以包括难熔金属如钨、掺杂或不掺杂的多晶硅、金属硅化物如硅化镍或硅化钨或这些材料的任意组合。为栅极68，69所选择的导体建立功函数，且因此影响完成的FinFET 72的阈值电压(Vt)。栅极68，69被绝缘覆层28的材料和半导体鳍片30的材料互相隔开。因此，在该分离栅极布置中，栅极68，69未被电连接，其中每个栅极68，69可以被独立地偏置，以控制FinFET 72的操作。
参考图13A，B，其中相同的参考标号指图12A，B中和后续制造阶段中的相同特征，通过蚀刻工艺剥离衬垫氮化物层14的剩余部分，该蚀刻工艺对构成氧化物层12和栅极68，69的材料具有选择性地除去衬垫氮化物层14的材料。例如，为了相对于氧化物和大多数栅极材料除去Si3N4，可以采用使用热酸如膦酸的湿法各向同性蚀刻工艺。但是，对于与用于栅极68的导体的其它材料的兼容性，也可以使用其它各向同性Si3N4蚀刻剂工艺，包括干法蚀刻工艺，如使用N2/Ar/CHF3化学物质的蚀刻剂的单步骤工艺，或使用CHF3+SF6+He的气体混合物的蚀刻化学物质，接着SF6+HBr+He气体蚀刻化学物质以及包括具有SF6+O2+He气体混合物的蚀刻化学物质的多步骤蚀刻工艺。
在除去衬垫氮化物层14之后，可以从源极和漏极区32，34的侧壁各向异性地蚀刻任意残留膜，以及由众所周知的方法如气相掺杂或离子注入引入源极-漏极掺杂。氧化物覆层28和栅极导体68，69防止FinFET 72(图14A，B)的沟道被源极-漏极掺杂污染。先前通过可选的沟道掺杂工艺引入源极-漏极区32，34中的任意沟道掺杂被浓度更高的源极-漏极掺杂有效地掩盖。源极-漏极区32，34的掺杂典型地将需要使用多个掩模，如光致抗蚀剂掩模，以引入不同的掺杂剂，从而形成N沟道FinFET＝s和P沟道FinFET＝s。
参考图14A，B，其中相同的参考标号指图13A，B中和后续制造阶段的相同特征，在限定FinFET 72的栅极结构的栅极68，69的垂直侧壁上形成例如Si3N4的可选隔离物70。隔离物70用于密封用于掺杂源极和漏极区32，34的源极-漏极扩散，用于完成FinFET 72的制造。隔离物70可以通过CVD氮化物层的保形淀积以及通过例如RIE工艺的定向除去来形成。绝缘填料74，如可回流玻璃如BPSG被淀积，以及通过常规平面化工艺如CMP平面化，以填充所有剩余的间隙。所得的半导体结构处于适合于常规处理的条件，该常规处理包括形成接触过孔和塞栓，多层构图金属化以及层间介质，以完成该集成电路。
本发明提供一种用于在公共体衬底10以及在SOI衬底(未示出)上集成平面器件42如CMOSFET＝s和FinFET＝s 72的工艺。FinFET 72的半导体鳍片30包括将鳍片30与衬底10电隔离的自对准隔离区24，通过注入适合于形成隔离区24的物质而提供。FinFET 72的鳍片30通过两个步骤工艺来形成，该工艺提供对由离子注入和退火形成的自对准隔离区24的分布的控制。
在制造过程中提供显著改进的机械完整性，这显著减小了处理过程中由支撑半导体鳍片30引起的鳍片断裂，以便鳍片30不是与常规技术一样的独立式和自立式。与特定的制造阶段无关，每个FinFET 72的鳍片30完全地或接近完全地被至少相邻的衬垫氮化物层14支撑。这保护薄的易毁坏鳍片30和由此避免在传统的制造方法过程中经历的断裂问题。FinFET＝s 72能够进行分离-栅极操作，其中施加到每个栅极68，69的电压可被独立控制。
FinFET 72的非平面器件构造或结构包括远离衬底10的平面凸出的中心垂直半导体鳍片30。每个FinFET 72的鳍片30包括中心沟道区64，被中心沟道区分开的源极和漏极区32，34，以及交叉半导体鳍片64的沟道区64的栅极68，69。半导体鳍片30具有小于最小光刻尺寸的宽度和高度与宽度的较高纵横比。每个平面器件42具有包括源极和漏极区50，52以及被覆盖栅极电极44控制的沟道54的一个水平主体部分。除栅极电极44之外，平面器件42的大多数元件包括源极和漏极区50，52以及沟道54在衬底10的表面15的平面中形成。
图15-20图示了在实践本发明的选择性实施例时涉及的制造阶段。在这些图中，标有“A”的视图是在一个制造阶段的半导体结构的顶视图，而标有“B”的视图是该半导体结构的剖面图。
根据本发明的选择性实施例和参考图15A，B，如关于图1A，B至图9A，B的上述处理进行工艺，以提供图15A，B所描绘的中间结构。但是，本发明的该实施例中的衬垫氧化物层12具有相对减小的垂直厚度，优选约1nm至约10nm。较薄的衬垫氧化物层12用作应力减轻层和粘附性促进剂，用于随后形成的衬垫氮化物层14。在本发明的该实施例中，衬垫氧化物层12太薄而不能形成用于半导体鳍片30的隔离，如图1A，B所示制成更厚的衬垫氧化物层12。衬垫氮化物层14具有50nm至约500nm的厚度以及最终决定半导体鳍片30的高度。
参考图16A，B，其中相同的参考标号指图15A，B中和后续制造阶段中的相同特征，有选择地除去衬垫氮化物层14至形成衬垫氧化物层12的材料和形成衬底10的材料。如果衬垫氮化物层14是Si3N4，衬垫氧化物层12是SiOx，以及衬底10是硅，那么可以用酸蚀刻剂如磷酸溶液的湿法蚀刻或利用CF3化学物质的干法蚀刻工艺除去衬垫氮化物层14。衬垫氮化物层14的除去露出半导体鳍片30。
在半导体鳍片30和源极和漏极区32，34周围的延伸的垂直侧壁上形成牺牲侧壁隔离物80。例如，侧壁隔离物80可以通过淀积CVD氮化物层至5nm至15nm的厚度以及执行适当的RIE工艺来形成。形成侧壁隔离物80的工艺可以在STI区36的垂直侧壁上形成外部隔离物。
通过适当的工艺如RIE工艺在衬底10中限定凹槽82，使衬底10的未保护部分被凹入。在未蚀刻的表面26下面，凹槽82的垂直深度优选在约20nm和约200nm之间。凹槽82的一部分围绕每个半导体鳍片30，以及也在源极和漏极区32，34周围延伸。在蚀刻过程中，侧壁隔离物80和保护绝缘覆层28掩蔽半导体鳍片30和垂直地在侧壁隔离物80下面的衬底10的区域。结果，凹槽82与鳍片30自对准。
参考图17A，B，其中相同的参考标号指图16A，B中和后续制造阶段的相同特征，介质层86如HDP氧化物被淀积到这样的厚度，其填充凹槽82至垂直地在衬垫氧化物层12的水平面上的水平。介质层86的材料主要地淀积在水平表面上。从半导体鳍片30的垂直侧壁98，100(图18A，B)和源极和漏极区32，34的侧壁以及任意其它垂直侧壁如STI区36除去来自层86的任意外部介质材料。例如，各向同性氧化物蚀刻可以除去介质层86的这些外部部分。介质层86与半导体鳍片30自对准，因为形成隔离凹槽82的制造步骤。部分介质层86也与每个鳍片30重叠。
优选，通过并行的介质层淀积和蚀刻工艺形成介质层86，在至少约10：1的水平表面与垂直表面上提供构成介质的厚度比。例如，可以通过由等离子体CVD工艺形成的HDP氧化物构成介质层86，所述工艺采用包含氧、硅烷和惰性气体如氩气的气体混合物，以实现同步介质蚀刻和淀积。惰性气体易于除去通过溅射淀积在垂直表面上的氧化物。
参考图18A，B，其中相同的参考标号指图17A，B中和后续制造阶段的相同特征，侧壁隔离物80(图17A，B)被有选择地除去至形成衬底10和介质层86的材料。在侧壁隔离物80被除去之后，可以通过例如气相掺杂剂扩散工艺或倾斜离子注入选择性地掺杂鳍片30的沟道区88。沟道区88的可选沟道掺杂典型地将需要使用多个掩模(未示出)，如光致抗蚀剂掩模，以在各个水平中引入不同的掺杂剂，以形成各种阈值电压的N沟道FinFET＝s和P沟道FinFET＝s。如果沟道区88中的半导体鳍片30的厚度足够地窄，那么沟道掺杂可以省略，因为在FinFET 106(图20A，B)的工作过程中，沟道区中的本征半导体材料被完全地耗尽。尽管在可选的沟道掺杂工艺过程中源极-漏极区32，34被露出，随后引入源极-漏极区32，34中的大量更高浓度掺杂将相对于引入沟道区88的较低掺杂剂浓度占主导。
参考图19A，B，其中相同的参考标号指图18A，B中和后续制造阶段的相同特征，在每个半导体鳍片30的沟道区88的露出相对侧壁100，102上形成栅极介质96。栅极介质96可以由任意常规的栅极绝缘体材料构成，包括但不限于SiOx、SiOxNy、Si3N4、高K介质如硅铪氮氧化物或其组合，如所属领域的普通技术人员所认识的。栅极介质96的厚度优选在约1nm至约6nm的范围内。
通过用适合的栅极导电材料的淀积层填充与介质层86重叠的凹槽82的部分，以及通过常规平面化工艺如CMP平面化至在平面MOSFET区42的水平面处建立的平面表面26，限定每个FinFET 106的栅极102，104。所属领域的普通技术人员公知这种工艺是镶嵌工艺。栅极导电材料可以包括难熔金属如钨、掺杂或不掺杂的多晶硅、金属硅化物如硅化镍或硅化钨或这些材料的任意组合。栅极导电材料的类型建立功函数且因此影响完成的FinFET 106的阈值电压(Vt)。然后栅极导电材料被构图，对氧化物覆层28和平面MOSFET区42具有选择性，通过常规光刻和蚀刻工艺，以限定栅极102，104。半导体鳍片30的每侧上的栅极102，104被绝缘覆层28的材料和半导体鳍片30的材料互相隔开。因此，在该分离-栅极布置中相对的栅极102，104未被电连接，其中每个栅极102，104可以被独立地偏置，以控制FinFet 106的操作。
现在通过众所周知的方法如气相掺杂或离子注入，源极-漏极掺杂被引入源极-漏极区32，34的露出侧壁。氧化物覆层28和栅极102，104防止FinFET 106的沟道区88被源极-漏极掺杂污染。先前通过可选的沟道掺杂工艺引入源极-漏极区32，34的任意沟道掺杂被大量更高浓度的源极-漏极掺杂有效地掩盖。源极-漏极区的掺杂典型地将需要使用多个掩模，如光致抗蚀剂掩模，以引入不同的掺杂剂，从而形成N沟道FinFET＝s和P沟道FinFET＝s。
参考图20A，B，其中相同的参考标号指图19A，B中和后续制造阶段的相同特征，淀积绝缘体层108，并通过常规平面化工艺如CMP平面化，以重建与氧化物覆层28的上水平表面和平面半导体器件42重合的平面表面26，绝缘体层108优选是可软回流和容易平面化的氧化物如BPSG、BSG、PSG或未密化的TEOS。残余绝缘体层108填充围绕平面半导体器件42和FinFET 106的缝隙空间。完成的半导体结构由平面半导体器件42和FinFET106构成，以及为常规处理准备横穿衬底10的表面复制的该组合结构的许多复制品，其可以包括形成接触过孔和塞栓，多层构图金属化和层间介质。
FinFET 106的沟道宽度与鳍片30的高度成正比，因为在FinFET器件中沟道宽度是垂直的。因此，沟道宽度近似等于被栅极介质96覆盖的鳍片30的高度，因此与栅极102，104隔开。因为用来形成介质层86的制造技术，FinFET 106的沟道宽度大于FinFET 72(图14A，B)的沟道宽度，这对于半导体结构的某些应用可能是有益的。
在此所指的术语如“垂直”、“水平”等是举例，而不是限制，以建立参照系。如在此使用的术语Ahorizontal≌被定义为平行于常规平面或衬底10的表面15的平面，与衬底10的实际空间取向无关。术语Avertical≌指垂直于水平的方向，仅仅作为限定。术语，如Aon≌、Aabove≌、Abelow≌、Aside≌(如Asidewall≌)、Ahigher≌、Alower≌、Aover≌、Abeneath≌和Aunder≌是相对于水平面而定义的。应当理解，在不脱离本发明的精神和范围的条件下，为了描述本发明可以采用各种其它参照系。
在此通过制造阶段和步骤的特定顺序描述了半导体结构的制造。但是，应当理解该顺序可以不同于所描述的那些顺序。例如，两个或以上的制造步骤的顺序可以相对于所示顺序切换。而且，可以同时进行或部分同时发生两个或以上的制造步骤。此外，各种制造步骤可以被省略及其它制造步骤可以被增加。应当理解所有的这种改变都本发明的范围内。还应当理解本发明的特征不必按图中的比例显示。
尽管通过各个实施例的描述说明了本发明，以及尽管非常详细地描述了这些实施例，但是申请人不打算限制或以任何方式限制附加权利要求的范围为这种详细描述。对所属领域的技术人员来说附加的优点和修改是显而易见的。因此，本发明在其更广泛的方面不局限于特定的细节、代表性装置和方法以及所示和描述的说明性例子。由此，从这种细节所进行的变更不脱离申请人的一般发明构思的精神或范围。

Claims (31)

1.一种半导体结构，包括：
单晶的体衬底；
多个平面器件，在所述单晶的体衬底中形成；以及
多个鳍片型场效应晶体管，每个与所述单晶的体衬底电隔离和与所述平面器件电隔离。
2.根据权利要求1的半导体结构，其中所述体衬底没有掩埋氧化物层。
3.根据权利要求1的半导体结构，还包括：
多个隔离区，每个在相应的一个所述鳍片型场效应晶体管和所述体衬底之间。
4.根据权利要求3的半导体结构，其中所述鳍片型场效应晶体管的每个包括半导体鳍片，相应的一个所述隔离区与所述半导体鳍片自对准。
5.根据权利要求1的半导体结构，其中所述平面器件是金属氧化物半导体场效应晶体管。
6.一种制造半导体结构的方法，包括以下步骤：
在衬底上的掩模中蚀刻第一沟槽；
在所述第一沟槽中形成半导体鳍片，所述半导体鳍片具有沟道区；
形成与所述半导体鳍片的所述沟道区交叉的栅极结构；以及
在形成所述栅极结构的同时用所述掩模支撑所述半导体鳍片。
7.根据权利要求6的方法，还包括以下步骤：
在部分形成所述半导体鳍片之后，在所述半导体鳍片和所述衬底之间形成隔离区。
8.根据权利要求6的方法，其中所述形成所述半导体鳍片的步骤还包括以下步骤：
执行选择性外延生长工艺，所述工艺在水平表面上以比在垂直表面上更大的生长速率淀积构成所述半导体鳍片的半导体。
9.根据权利要求6的方法，其中所述形成所述栅极结构的步骤还包括以下步骤：
在所述掩模中蚀刻延伸至所述衬底的第二沟槽，所述第二沟槽暴露所述沟道区；以及
在所述第二沟槽中形成所述栅极结构。
10.根据权利要求9的方法，还包括以下步骤：
掺杂所述暴露的沟道区；以及
在掺杂所述暴露的沟道区的同时用所述掩模支撑所述半导体鳍片。
11.根据权利要求9的方法，其中所述形成所述栅极结构的步骤还包括以下步骤：
在所述沟道区的第一侧壁侧面的所述第二沟槽的第一部分中形成第一栅极；以及
在所述沟道区的第二侧壁侧面的所述第二沟槽的第二部分中形成第二栅极，所述第一栅极与所述第二栅极电隔离。
12.根据权利要求11的方法，还包括以下步骤：
在形成所述第一栅极之前，在所述第一侧壁上形成第一栅极介质；以及
在形成所述第二栅极之前，在所述第二侧壁上形成第二栅极介质。
13.根据权利要求6的方法，其中通过镶嵌工艺形成所述栅极结构。
14.根据权利要求6的方法，其中通过镶嵌工艺形成所述半导体鳍片。
15.根据权利要求6的方法，还包括以下步骤：
形成与所述半导体鳍片相邻的平面器件。
16.根据权利要求15的方法，其中所述平面器件是金属氧化物半导体场效应晶体管。
17.一种制造半导体结构的方法，包括以下步骤：
在覆盖衬底的掩模中蚀刻沟槽；
在所述沟槽中形成第一外延层；
穿过所述掩模将离子注入所述第一外延层中，以便所述沟槽使所述注入的离子与所述第一外延层自对准；
将所述注入的离子转变为将所述第一外延层与所述衬底电隔离的掩埋隔离区；以及
在所述沟槽中和所述第一外延层上形成第二外延层。
18.根据权利要求17的方法，其中所述半导体鳍片和所述衬底包括硅，以及所述掩埋隔离区包括氧和硅，以及所述将离子注入所述第一外延层中的步骤还包括以下步骤：
将含氧离子注入所述外延层中。
19.根据权利要求17的方法，其中在所述外延层和所述衬底之间限定一界面，以及所述将离子注入所述第一外延层中的步骤还包括以下步骤：
选择离子能量，以便离子范围接近所述界面。
20.根据权利要求17的方法，其中所述衬底是单晶，以及所述沟槽延伸至所述衬底，以及所述形成所述第一外延层的步骤还包括以下步骤：
使用所述衬底作为形成所述第一外延层的籽晶。
21.根据权利要求17的方法，其中所述形成所述第二外延层的步骤还包括以下步骤：
使用所述第一外延层作为形成所述第二外延层的籽晶。
22.根据权利要求17的方法，其中通过热处理将所述注入的离子转变为所述掩埋隔离区。
23.根据权利要求22的方法，其中所述热处理退火由所述离子注入在所述第一外延层中产生的损伤，以及还包括以下步骤：
使用所述第一外延层作为形成所述第二外延层的籽晶。
24.一种制造半导体结构的方法，包括以下步骤：
形成从衬底凸出的半导体鳍片；
蚀刻围绕所述半导体鳍片的所述衬底的部分，以在所述半导体鳍片的基底周围的所述衬底中限定凹槽；以及
用介质材料至少部分地填充所述凹槽，以使所述半导体鳍片与所述衬底电隔离。
25.根据权利要求24的方法，还包括以下步骤：
在蚀刻围绕所述半导体鳍片的所述衬底的部分之前，在所述半导体鳍片上形成侧壁隔离物。
26.根据权利要求25的方法，还包括以下步骤：
在蚀刻围绕所述半导体鳍片的所述衬底的部分之后，从所述半导体鳍片除去所述侧壁隔离物。
27.根据权利要求24的方法，还包括以下步骤：
在蚀刻围绕所述半导体鳍片的所述衬底的部分之前，形成所述半导体鳍片的保护覆层。
28.根据权利要求24的方法，其中通过镶嵌工艺形成所述半导体鳍片，以及在蚀刻围绕所述半导体鳍片的所述衬底的部分之前，除去用于形成所述半导体鳍片的构图掩模。
29.根据权利要求24的方法，其中绝缘层将所述半导体鳍片与所述衬底隔开，以及所述介质材料填充所述凹槽至所述绝缘层之上的高度。
30.根据权利要求24的方法，其中所述半导体鳍片包括沟道区，以及还包括以下步骤：
掺杂所述沟道区；以及
在用导体填充与所述鳍片相邻的区域之前，在所述半导体鳍片的第一和第二侧壁上形成栅极介质。
31.根据权利要求30的方法，还包括以下步骤：
构图和蚀刻所述导体，以形成与所述沟道区的第一侧壁相邻的第一栅极；以及
形成与所述沟道区的第二侧壁相邻的第二栅极，所述第一栅极与所述第二栅极电隔离。
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