TWI517262B - 整合鑲嵌體鰭式場效電晶體與平面裝置於共同基板上的半導體結構及其形成方法 - Google Patents

整合鑲嵌體鰭式場效電晶體與平面裝置於共同基板上的半導體結構及其形成方法 Download PDF

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TWI517262B
TWI517262B TW101133113A TW101133113A TWI517262B TW I517262 B TWI517262 B TW I517262B TW 101133113 A TW101133113 A TW 101133113A TW 101133113 A TW101133113 A TW 101133113A TW I517262 B TWI517262 B TW I517262B
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epitaxial layer
substrate
forming
trench
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羅格 艾倫 伯思二世
傑克 艾倫 曼得門
威廉 羅伯 頓
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萬國商業機器公司
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Description

整合鑲嵌體鰭式場效電晶體與平面裝置於共同基板上的半導體結構及其形成方法
本發明係關於半導體結構，且特別關於一整合鑲嵌體鰭式場效電晶體與平面互補金氧半導體裝置於共同基板上的半導體結構及形成此類半導體結構的方法。
逐漸縮小化電路元件的特徵尺寸已改善積體電路的效能且增加功能性。鰭式(fin-typed)場效電晶體(FinFETs)是低耗電以及高速電晶體，且可密集排列在一基板上。然而，鰭式場效電晶體並不是適合積體電路設計的所有目。不同應用情形需要不同的電晶體裝置行為。在操作期間，鰭式場效電晶體為完全空乏，是許多應用所期望的。然而，電路設計也需要習知裝置例如金氧半導體場效電晶體(MOSFETs)，其並非為完全空乏。
通常，習知鰭式場效電晶體結構包含一中央垂直半導體鰭與一主體，其包含中央通道區域、於垂直半導體鰭的相對端並由中央通道區域隔開之源極與汲極，以及覆蓋通道區域的閘極導體層。半導體鰭通常具有一少於最小微影尺寸的寬度，以及相當高的深寬比(aspect ratio)。
在習知鰭式場效電晶體結構，半導體鰭是獨立的而且在製程期間不受周圍元件結構所支撐。結果，在製程步驟期間，例如超音波擾動，獨立且未受支撐的半導體鰭有斷裂的顯著危險。形成鰭式場效電晶體結構的製程期間可能形成劇烈溫度變化，使得脆弱未受支撐的半導體鰭因熱效應而破裂。
絕緣層上矽(SOI)基板已知包含鰭式場效電晶體與平面MOSFETs，其中鰭式場效電晶體的半導體鰭係使用絕緣層上矽基板的結晶矽作為晶種層，而透過溝槽形成。然而，因為隔離問題，這些習知製造技術專門使用於絕緣層上矽(SOI)基板，其中SOI層的結晶矽係藉由埋式絕緣層與基板下方部分電性隔離。因此，這些製造技術不適用於整合鰭式場效電晶體(FinFETs)與平面裝置(例如MOSFETs)於一共同塊基板(common bulk substrate)上。
因此，需要包含鑲嵌體鰭式場效電晶體與平面互補金氧半導體裝置之塊基板，以及形成鑲嵌體FinFET及平面MOSFET於共同塊基板或SOI基板之方法，以克服習知基板缺點及其製造此類基板方法的缺點。
本發明係相關於將鑲嵌體鰭式場效電晶體與平面互補金氧半導體裝置整合在共同基板上。根據本發明之一方面，一半導體結構包含一單晶塊基板、數個平面裝置設置於單晶塊基板、以及數個鰭式場效電晶體。每個鰭式場效電晶體與單晶塊基板隔離且與平面裝置電性隔離。
本發明的另一方面係提供一種製造半導體結構之方法，包含蝕刻一溝槽於一遮罩中以及形成一半導體鰭於溝槽中。本方法更包含當形成與半導體鰭相交之閘極結構時，以遮罩支撐半導體鰭。
本發明的另一方面係提供一製造半導體結構之方法，包含於覆蓋一基板的一遮罩中，蝕刻一溝槽；形成一第一磊晶層於溝槽中；以及經由該遮罩，植入離子入第一磊晶層，使得溝槽將植入離子與第一磊晶層自我對準。本方法更包含將植入離子轉換成一埋式隔離區域，以電性隔離第一磊晶層與基板；以及然後形成一第二磊晶層於溝槽中且在第一磊晶層上。
本發明的其他方面係提出一形成半導體結構之方法，包含形成突出於一基板之一半導體鰭，並蝕刻環繞半導體鰭的基板部份，以界定一凹陷於基板內，約於半導體鰭的基部附近。本方法更包含以一介電材料至少部份地填塞凹陷，以電性隔離半導體鰭與基板。
本發明提出一種半導體結構，將鰭式場效電晶體(FinFET)與平面互補金氧半導體裝置(CMOS)，例如場效電晶體整合在一共同基板上，或在絕緣層上矽(SOI)基板上。本發明也提出一種製造這些結構之方法，並且將參閱本發明圖式詳細說明。
圖1-14顯示本發明實施例的製造步驟。在圖式中，標示為“A”的視圖係為在製造階段，半導體結構之俯視圖，而且標示為“B”的視圖係半導體結構的截面圖。
參閱圖1A與1B，顯示本發明一實施例初始製造階段提供 或獲得的單晶基板10。基板10可為任何類型的習知單晶半導體基板，例如所示的塊矽基板，或者絕緣層上矽(SOI)基板的主動層。具有相當厚的墊氧化層12(SiOx)形成在基板10的暴露表面15上。墊氧化層12藉由習知熱化學氣相沉積(CVD)製程而沉積，或者藉由濕或乾熱氧化製程而形成。墊氧化層12隨即部分形成對於半導體鰭30(圖6A與6B)的隔離，因而將降低寄生閘極電容。墊氧化層12的垂直厚度較佳約為50奈米(nm)至大約200奈米。
墊氮化層14形成在墊氧化層12上。墊氮化層14包含氮化矽(Si3N4)，且經由習知沉積製程例如化學氣相沉積(CVD)製程或電漿輔助化學氣相沉積(CVD)製程而形成。墊氮化層14的硬度與耐磨性在後續製程步驟足以充當一硬遮罩以及研磨停止層。形成墊氮化層14的材料也必須與墊氧化層12具有蝕刻選擇性。墊氮化層14的垂直厚度決定半導體鰭的高度，且較佳約為50nm至大約500nm。
參閱圖2A與2B，其中相似元件符號指向圖1A與1B的相似元件，而且在隨後製造步驟中，圖案化開口或溝槽16藉由習知微影與蝕刻方法形成在墊氧化層12與墊氮化層14中。溝槽16由實質平坦表面26垂直延伸至基板10的深度，而且在此製造步驟中，平坦表面26定義為墊氮化層14的頂部水平表面。應該注意，雖然圖式顯示形成單一溝槽16，但是本發明可在半導體結構形成數個溝槽16。在以後製造步驟中，每個溝槽16最終界定鰭式場效電晶體(FinFET)72(圖14A與14B)的鰭30(圖6A與6B)以及源極與汲極區域32、34(圖6A與6B)。
溝槽16的圖案，每個為典型H狀，且可由習知微影技術形成，其塗佈光阻(未繪示)於墊氮化層14的表面、將光阻暴露於具有圖案的輻射線、且顯影已曝光光阻轉移圖案。適當微影技術包含具有或不具有相位移的微影、X射線微影、電子束微影或者側壁影像轉移的組合等，以形成鰭30的溝槽16，並且使用習知微影形成溝槽16的另一部份，用於界定FinFET72(圖14A與14B)的源極與汲極區域32、34(圖6A與6B)。
對於墊氧化層12材料具有選擇性的習知非等向乾蝕刻製程，例如反應式離子蝕刻(RIE)或電漿蝕刻，用於轉移溝槽圖案至墊氮化層14而且到達墊氧化層12的深度。蝕刻製程的化學作用以單一蝕刻步驟或數個蝕刻步驟實施，而且移除透過溝槽圖案可見的墊氮化層14的部分，並且蝕刻製程的化學作用將垂直停止在墊氧化層12。溝槽圖案藉由對於基板10材料具有選擇性之其他非等向乾蝕刻，例如活性離子蝕刻(RIE)或電漿蝕刻，而延伸至基板10的深度。蝕刻製程的化學作用以單一蝕刻步驟或數個蝕刻步驟實施，而且移除透過具有圖案的墊氮化層14為可見的墊氧化層12部分，並且蝕刻製程的化學作用垂直停止在基板10。
參閱圖3A與3B，其中相似元件符號指向圖2A與2B的相似元件，而且在隨後製造步驟中，適當材料(例如矽)的磊晶層18選擇性形成在每個溝槽16內。磊晶層18不完全填滿溝槽16，而是垂直延伸僅部份填充溝槽16。較佳地，磊晶層18的垂直高度係介於大約25nm至大約100nm。在每個溝槽16 底部的基板10的暴露表面做為晶體成長的晶種，而且藉由提供磊晶層18的材料成長樣板(template)而決定磊晶層18的結晶方向性。較佳地，形成磊晶層18的半導體材料在墊氧化層12與墊氮化層14(係在磊晶層18垂直高度上環繞每個溝槽16)的垂直表面不形成明顯厚度。在基板10與磊晶層18間形成電性隔離層後，磊晶層18的成長在後續製造步驟將持續進行，如後詳述。
適合用於形成磊晶層18的製程是選擇性的磊晶成長(SEG)製程，可在次大氣壓製程壓力且基板溫度在大約850℃與大約1050℃間實施。典型製程條件是大約40 torr以及大約900℃。選擇性磊晶成長(SEG)製程的矽來源包含，但不限於：四氯化矽(SiCl4)、三氯矽烷(SiHCl3)以及二氯矽烷(SiH2Cl2)。矽來源存在的氯增加用於限制在磊晶層18垂直高度上環繞每個溝槽16之墊氧化層12與墊氮化層14的區域成長之選擇性。選擇性成長(selective growth)維持磊晶層18材料的結晶結構，而不形成對於鰭式場效電晶體(FinFET)72(圖14A與14B)具有危害的顯著晶體缺陷。
參閱圖4A與4B，其中相似元件符號指向圖3A與3B的相似元件，而且在隨後製造步驟中，對於磊晶層18進行離子植入，約正向植入含氧離子20，例如原子的或分子的氧離子。離子植入能量導致氧濃度分佈22在相當淺的深度，該濃度分佈相關於離子範圍垂直方向分佈。氧濃度分佈22的最終峰值濃度(peak concentration)大約位於基板10與磊晶層18間介面，而且與墊氧化層12重疊。例如，O+物種的離子20可以大 約25keV至大約100keV範圍間能量以及大約在2x1017cm-2至大約在5x1018cm-2範圍間離子劑量植入。在往後製造步驟中，氧濃度分佈22轉換成埋式隔離區域24(圖5A與5B)，且位於半導體鰭30下方，將半導體鰭30與基板10隔離。根據本發明，可植入其他離子物種，其可加入氧離子或取代氧離子，亦可提供半導體鰭30所需的電性隔離。
含氧離子20經由墊氧化層12與墊氮化層14的溝槽16植入，並且相對於半導體鰭30自我對準埋式隔離區域24。用於遮蔽基板10之每個開放溝槽16的側壁17，實質界定埋式隔離區域24的側向部份。雖然含氧離子20以幾乎正向植入磊晶層18，但是激態離子20的側向離散(lateral straggle)使得氧濃度分佈22，以垂直突出側壁17側向延伸至基板10而且進入墊氧化層12，因此係為垂直離子植入方向。
在暫停磊晶層18的成長後，以低植入能量透過磊晶層18植入含氧離子20，以限制磊晶層18的氧濃度分佈22的垂直離子離散(ion straggle)。假如磊晶層18完全充滿每個溝槽16，則需要明顯較高的植入能量，這將引起磊晶層18的晶格受損增加，而且因為增加的垂直離子離散，使得氧濃度分佈22最終深度的控制變得困難。氧濃度分佈22上方的磊晶層18幾乎是沒有受損的(damage-free)，而後在隨後製造步驟中可作為晶種層，以便持續層18的磊晶成長。
參閱圖5A與5B，其中相似元件符號指向圖4A與4B的相似元件，而且在隨後製造步驟中，磊晶層18在適當氣壓例 如鈍氣環境或真空下熱處理或進行退火，以移除植入離子對磊晶層18造成的離子引致損害。退火製程實施於基板溫度約1100℃至約1300℃間，而且完全形成埋式隔離區域24，係藉由磊晶層18及基板10的氧濃度分佈22所界定的富含氧(oxygen-rich)材料接合(coalesce)，而界定隔離區域24。
參閱圖6A與6B，其中相似元件符號指向圖5A與5B的相似元件，而且在隨後製造步驟中，在退火製程結束後，恢復磊晶層18的選擇性成長。例如，前述恢復成長的製程可使用例如選擇性磊晶成長(SEG)製程，以沉積用於構成磊晶層18之材料的添加厚度。磊晶層18初始形成的部份作為恢復成長製程的晶種，針對新加入材料的成長提供一樣板，且在新加入材料中複製樣板，使得初始結晶結構存在於新加入材料。形成磊晶層18突出墊氮化層14的頂部水平面以達到一垂直高度。藉由平坦化製程例如化學機械研磨(CMP)製程，使得磊晶層18的頂部水平表面與墊氮化層14的頂部水平表面實質上共平面，以重建實質平坦表面26以及完成鑲嵌製程(damascene)。此類習知化學機械研磨(CMP)製程係結合研磨與溶解作用，以移除殘留在墊氮化層14上磊晶層18的過多材料，而且垂直地方停止在墊氮化層14上。
平坦化的磊晶層18藉由非等向性乾蝕刻製程，相對於平坦表面26，凹化至大約10nm至100nm。絕緣毯覆層(例如化學氣相沉積(CVD)氧化層)隨後形成在平坦表面26上。平坦表面26的實質平坦度藉由平坦化製程例如化學機械研磨(CMP)製程再次達成，這移除絕緣毯覆層的過多部份且停止在墊氮化 層14的頂部水平表面。絕緣層的殘留部分填塞磊晶層18各凹陷區域上的空間，且因此於行程磊晶層18的材料上方形成保護絕緣蓋28。
在各溝槽16的磊晶層18界定薄的中央半導體主體或鰭30以及源極與汲極區域32、34，其包含鰭30的相對端之放大接點。鰭30由基板10的介面垂直突出，且藉由墊氧化層12材料與構成墊氮化層14的材料橫向地支撐。
參閱圖7A與7B，其中相似元件符號指向圖6A與6B的相似元件，而且在隨後製造步驟中，淺溝槽隔離(STI)區域36藉由習知微影與蝕刻方法形成在基板10的各個位置，其包含利用遮蔽平坦表面26與蝕刻，例如反應式離子(RIE)蝕刻或電漿蝕刻。溝槽(圖7A與7B)穿過墊氧化層12與墊氮化層14且持續入基板10達一淺深度。蝕刻入基板10後，可應用選擇性襯層(未顯示)於溝槽。沉積適用於淺槽絕緣(STI)區域36的絕緣毯覆層，例如四乙基正矽酸鹽(TEOS)或高密度電漿(HDP)氧化物之類的化學氣相沉積(CVD)氧化物，以填塞溝槽。平坦表面26的實質平坦度藉由習知平坦化製程例如化學機械研磨(CMP)製程再次達成，這移除絕緣毯覆層的過多部份且停止在墊氮化層14的頂部水平表面。
參閱圖8A與8B，其中相似元件符號指向圖7A與7B的相似元件，而且在隨後製造步驟中，阻擋遮罩38使用在平坦表面26，以覆蓋與保護磊晶層18與環繞磊晶層18的硬遮罩層部份。接著非等向性乾蝕刻製程用於移除未受阻擋遮罩38 保護的墊氧化層12與墊氮化層14之部份，以使得凹陷區域40暴露出來，其開放基板10以用於後續製造平面裝置。第一次非等向性乾蝕刻製程對墊氧化層12材料有選擇性，係移除墊氮化層14材料。第二次非等向性乾蝕刻製程對墊氮化層14材料有選擇性，係移除墊氧化層12材料。阻擋遮罩38係不需要與淺溝槽絕緣(STI)區域36重疊，但是必須覆蓋後續用於形成鰭式場效電晶體(FinFET)72(圖14A及14B)之區域，以避免蝕刻保護絕緣蓋28。在界定凹陷區域40後，剝除阻擋遮罩38以暴露出淺溝槽隔離(STI)區域36，這些區域的平坦度因凹陷區域40的存在而受到影響。
參閱圖9A與9B，其中相似元件符號指向圖8A與8B的相似元件，而且在隨後製造步驟中，平面半導體裝置42(通常以參考標號42指示，且用以討論繪示為金氧半導體場效電晶體(MOSFET))藉由習知步驟形成在各凹陷區域40。裝置42包含閘電極44，其藉由一薄閘極介電層46與基板10分隔。閘電極44可為高度導電摻雜的多晶矽，或者由一或多種金屬製成，例如鉬(molybdenum)、鈦(titanium)、鉭(tantalum)或鎳、金屬矽化物或金屬氮化物。薄閘極介電層46包含由乾燥氧氣或蒸氣成長的氧化物(例如二氧化矽(SiO2))、或包含其他材料例如氮化矽(Si3N4)、氮氧化矽(SiOxNy)或二氧化矽與氮化矽的閘極介電層堆疊，或包含類似五氧化二鉭(Ta2O5)的金屬氧化物。
側壁間隙壁48形成在閘電極44的側壁以及其他暴露的垂直表面上，且側壁間隙壁48由例如氮化矽(Si3N4)材料形成。閘電極44及/或側壁間隙壁48可作為一或數個離子植入製程 的自我對準遮罩，以形成源極50與汲極52。將摻雜質植入以形成源極50與汲極52的技術，對於熟習此技藝人士是熟悉的。選替地，源極與汲極50、52可藉由摻雜質擴散或摻雜質擴散與離子植入製程的組合而形成。位於源極50與汲極52間的基板10部份包含一通道54，而通道54的阻值藉由電源傳送至閘電極44的電壓加以控制，而且閘電極44經由薄閘極介電層46與通道54形成靜電地耦合。最後，絕緣層56較佳是一種軟且可流動以及容易平坦化的氧化物，例如硼磷矽酸鹽玻璃(BPSG)、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)或四乙基正矽酸鹽(TEOS)。沉積絕緣層56以填塞各凹陷區域40的其餘開放空間。絕緣層56藉由習知平坦化製程例如化學機械研磨(CMP)平坦化，以重建平坦表面26的實質平坦度達墊氮化層14的水平表面。
參閱圖10A與10B，其中相似元件符號指向圖9A與9B的相似元件，而且在隨後製造步驟中，閘極溝槽58藉由習知微影與蝕刻製程形成在墊氮化層14，其中墊氮化層14的部份區域經由可移除保護遮罩(未顯示)的圖案化開孔而暴露出來，且利用對墊氧化層12有選擇性的反應式離子蝕刻或電漿蝕刻移除。每個閘極溝槽58延伸至墊氧化層12的垂直高度。閘極溝槽58接著藉由部份導體填塞，使得每個鰭式場效電晶體(FinFET)72具有一組閘極68、69(圖14A與14B)。半導體鰭30的相對垂直側壁60、62暴露構成磊晶層18半導體材料的通道區域64。源極與汲極區域32、34仍然由墊氮化層14覆蓋與保護。除沿著垂直側壁60、62暴露的半導體鰭30長度部份之外，半導體鰭30的其餘部份依舊受到墊氧化層12與墊氮 化層14支撐。
通道區域64可經由氣相摻雜質擴散製程或傾角離子植入製程做選擇性摻雜。通道區域64的選擇性摻雜過程一般需要使用數個遮罩(未顯示)，例如光阻遮罩，以導入多種濃度的不同摻雜質而形成多種臨限電壓的P型通道FinFET與N型通道FinFET。假如通道區域64的半導體鰭30夠狹窄，而且鰭式場效電晶體(FinFET)的操作期間，通道區域64在完全空乏(fully-deleted)狀態，則可省略摻雜通道的製程。
參閱圖11A與11B，其中相似元件符號指向圖10A與10B的相似元件，而且在隨後製造步驟中，閘極介電層66形成在各半導體鰭30通道區域64之暴露出的相對垂直側壁60、62。閘極介電層66包含任意習知閘極絕緣層材料，包含但不限於：氧化矽(SiO2)、氮氧化矽(SiOxNy)、氮化矽(Si3N4)、高介電常數(high-K)介電質例如矽氮氧鉿(silicon hafnium oxynitride)或其組合等，熟習此技藝人士應該明瞭這些材料。閘極介電層66的厚度較佳在大約1 nm至大約6 nm。
參閱圖12A與12B，其中相似元件符號指向圖11A與11B的相似元件，而且在隨後製造步驟中，形成鰭式場效電晶體(FinFET)72(圖14A與14B)的閘極68、69，這藉由沉積一閘極導體以填塞各閘極溝槽58，隨後使用習知平坦化製程例如化學機械研磨平坦化閘極導體以重建平坦表面26的實質平坦度，並且化學機械研磨製程停止在墊氮化層14。熟習此技藝人士視此種製程為鑲嵌製程(damascene process)。閘極導體 68、69可包含如鎢的反射金屬、摻雜或未摻雜的多晶矽、如矽化鎳(Nickel Silicide)或矽化鎢(Tungsten Silicide)的金屬矽化物或者這些材料的組合。選作為閘極68、69的導體建構功函數(work function)，以影響完成的鰭式場效電晶體(FinFET)72的臨限電壓(Vt)。閘極68、69彼此分隔，係藉由保護絕緣蓋28與半導體鰭30材料。結果，閘極68、69以此分裂閘極型式(split-gate arrangement)並不電性連接，其中各閘極68、69可分別偏壓控制鰭式場效電晶體(FinFET)72。
參閱圖13A與13B，其中相似元件符號指向圖12A與12B的相似元件，而且在隨後製造步驟中，墊氮化層14的其餘部份由蝕刻製程清除，其係對墊氧化層12與閘極68、69有選擇性而移除墊氮化層14。例如，濕等向性蝕刻製程使用熱酸液例如磷酸，可相對於氧化層與多數閘極材料移除氮化矽(Si3N4)。然而，為配合閘極68使用的其他相容材料，亦可使用其他等向性Si3N4蝕刻劑製程，包含使用N2/Ar/CHF3蝕刻劑的單一步驟蝕刻製程，或者多步驟蝕刻製程，係使用CHF3+SF6+He的混合氧體蝕刻劑，接著使用SF6+HBr+He的氣態蝕刻劑且最後具有SF6+O2+He混合氣體的蝕刻劑。
移除墊氮化層14後，任何剩餘薄層由源極與汲極區域32、34的側壁進行等向性蝕刻，而且以習知方式例如氣相摻雜或離子植入製程進行源極-汲極摻雜過程。氧化物帽蓋28與閘極導體68、69保護鰭式場效電晶體(FinFET)72(圖14A及14B)的通道避免受到源極-汲極摻雜過程污染。先前選擇性通道摻雜導入源極與汲極區域32、34的任何通道摻雜，係藉由較高 濃度源極-汲極摻雜有效地掩蓋。源極與汲極區域32、34的摻雜過程通常使用數個遮罩例如光阻遮罩，導入不同摻雜質以形成P型通道FinFET與N型通道FinFET。
參閱圖14A與14B，其中相似元件符號指向圖13A與13B的相似元件，而且在隨後製造步驟中，例如氮化矽(Si3N4)的間隙壁70形成在界定鰭式場效電晶體(FinFET)72的閘極結構之閘極68、69的垂直側壁。間隙壁70囊封源極-汲極擴散區，用以摻雜源極與汲極區域32、34完成鰭式場效電晶體(FinFET)72的製程。間隙壁70可由化學氣相沉積(CVD)氮化層以及反應式離子蝕刻(RIE)製程的方向性移除製程而形成。沉積絕緣填塞料74例如可流動玻璃，如硼磷矽酸鹽玻璃(BPSG)，且經由習知平坦化製程例如化學機械研磨(CMP)以填塞所有剩餘空隙。最後半導體結構適合用於習知製程，這些製程包含形成接觸介層/柱體、多層圖案金屬化以及層間介電層，以完成積體電路。
本發明提出一種整合平面裝置，例如平面互補金氧半導體裝置場效電晶體(CMOSFET)與鰭式場效電晶體(FinFET)在一共同塊基板10與絕緣層上矽(SOI)(未繪示)。藉由植入一適當摻雜質以形成埋式隔離區域24，鰭式場效電晶體(FinFET)72的半導體鰭30包含自我對準的埋式隔離區域24，使得半導體鰭30與基板10電性隔離。鰭式場效電晶體(FinFET)72的半導體鰭30經由兩步驟製程形成，而且該製程用以控制藉由離子植入製程與退火製程形成的自我對準埋式隔離區域24的輪廓。
製造期間形成明顯改善的機械整體性，並且製程期間因為支撐半導體鰭30明顯降低斷裂情形，因半導體鰭30不是自由站立(free standing)而是在自我支撐狀態(self-supporting)。不論特定製造階段，鰭式場效電晶體(FinFET)72的半導體鰭30不是完全就是近乎完全至少受到鄰近墊氮化層14的支撐。如此可保護半導體鰭30避免在習知製造方法所造成的斷裂問題。鰭式場效電晶體(FinFET)72具有分裂閘極操作，其中可單獨控制施加在各閘極68、69的電壓。
非平面裝置架構或鰭式場效電晶體(FinFET)72結構包含中央垂直的半導體鰭30，其由基板10平面向外突出。各鰭式場效電晶體(FinFET)72的鰭30包含中央通道區域64、源極與汲極區域32、34以及閘極68、69。源極與汲極區域32、34藉由中央通道區域64分隔開，而且閘極68、69與半導體鰭30的通道區域64相交。半導體鰭30具有小於最小微影尺寸的寬度，以及相對較高的深寬比。各平面半導體裝置42具有單一水平主體部份，包含源極與汲極50、52及通道54，而且通道54受到上方閘電極44控制。除閘電極44外，平面半導體裝置42的大部份元件包含源極50、汲極52與通道54係建構在基板10表面15平面上。
圖15-20是顯示本發明另一實施例之製程階段。在圖式中，“A”是一製造階段的半導體結構的俯視圖，而且“B”是半導體結構的截面圖。
根據本發明實施例而且參閱圖15A、15B，製程由圖1A、1B持續進行至圖9A、9B，以提供圖15A、15B的半導體結構的中間結構。然而，本發明實施例的墊氧化層12具有相對較小的垂直厚度，而且厚度較佳大約1 nm至大約10 nm。相當薄的墊氧化層12作為後續形成的墊氮化層14之應力減輕層與附著性提升層。根據本發明此實施例，墊氧化層12太薄以致於無法對半導體鰭30形成隔離，而如圖1A、1B的較厚的墊氧化層12。墊氮化層14具有50 nm至大約500 nm的厚度，且最終決定半導體鰭30的高度。
參閱圖16A與16B，其中相似元件符號指向圖15A與15B的相似元件，而且在隨後製造步驟中，相對於墊氧化層12材料與形成基板10的材料，選擇性移除墊氮化層14。假如墊氮化層14是氮化矽(Si3N4)，墊氧化層12是氧矽化物(SiOx)而基板10是矽，墊氮化層14可在磷酸溶液的蝕刻劑以濕蝕刻進行移除，或者以CF3化學劑進行乾蝕刻。移除墊氮化層14使得半導體鰭30暴露出來。
犧牲側壁間隙壁80形成在垂直側壁，延伸至半導體鰭30以及源極與汲極區域32、34附近。例如，藉由沉積具有5 nm至15 nm厚度的化學氣相沉積製程(CVD)氮化層，而且經由適當反應式離子蝕刻製程(RIE)製程，以形成側壁間隙壁80。形成側壁間隙壁80的製程在淺溝槽隔離(STI)區域36的垂直側壁上形成外部間隙壁。
藉由適當製程例如反應式離子蝕刻(RIE)製程，界定凹陷 82於基板10內，此製程係凹化基板10未受保護的區域。凹陷82的垂直深度較佳為平坦表面26下方約20 nm與大約100 nm間。部份凹陷82環繞半導體鰭30，且延伸至源極與汲極區域32、34附近。蝕刻製程期間，側壁間隙壁80與保護絕緣蓋28遮蔽半導體鰭30以及在側壁間隙壁80垂直下方基板10的區域。結果，凹陷82與半導體鰭30是自我對準的。
參閱圖17A與17B，其中相似元件符號指向圖16A與16B的相似元件，而且在隨後製造步驟中，介電層86例如高密度電漿(HDP)氧化物，以填塞凹陷82至墊氧化層12水平位置上的垂直高度的厚度沉積。介電層86材料主要沉積在水平表面上。由半導體鰭30的垂直側壁98、100(圖18A、18B)、源極與汲極區域32、34的側壁，以及其他垂直側壁例如淺溝槽隔離(STI)區域36，移除介電層86的過多材料。例如，等向性氧化層蝕刻製程可移除介電層86的多於部分。因為形成隔離凹陷82的製造步驟，介電層86是自我對準於半導體鰭30。部份的介電層86也位於各半導體鰭30上。
介電層86較佳藉由同時發生的介電層沉積與蝕刻製程而形成，且該製程提供水平表面的介電層厚度與垂直表面的介電層厚度比率至少大約為10：1。例如，介電層86可為電漿化學氣相沉積(CVD)製程形成的高密度電漿(HDP)氧化物，而電漿化學氣相沉積(CVD)製程使用含有氧氣、矽烷與惰性氣體例如氬氣的混合氣體，以達成同時介電層蝕刻與沉積。藉由濺鍍製程，惰性氣體用於移除沉積在垂直表面的氧化層。
參閱圖18A與18B，其中相似元件符號指向圖17A與17B的相似元件，而且在隨後製造步驟中，相對於形成基板10與介電層86的材料，選擇性移除側壁間隙壁80(圖17A與17B)。在移除側壁間隙壁80後，半導體鰭30的通道區域88經由氣相摻雜質擴散製程或傾角離子植入製程選擇性摻雜。摻雜通道區域88的摻雜過程需要使用數個遮罩(未顯示)，例如光阻遮罩以導入多種濃度的不同摻雜質而形成多種臨限電壓的P型通道FinFET與N型通道FinFET。假如通道區域88的半導體鰭30夠窄，而鰭式場效電晶體106(圖20A與20B)的操作期間，通道區域88在完全空乏狀態，則可省略通道的摻雜製程。雖然在選擇性通道摻雜製程期間，源極-汲極區域32、34為暴露的，後續導入源極-汲極32、34的較高濃度摻雜將控制導入通道區域88中相對低的摻雜值濃度。
參閱圖19A與19B，其中相似元件符號指向圖18A與18B的相似元件，而且在隨後製造步驟中，一閘極介電層96形成在各半導體鰭30的通道區域88之暴露的相對側壁100、102上。閘極介電層96可包含任意習知閘極絕緣層材料，包含但不限於：氧化矽(SiO2)、氮氧化矽(SiOxNy)、氮化矽(Si3N4)、高介電常數(high-K)介電質例如矽氮氧鉿或其組合等，熟習此技藝人士應該明瞭這些材料。閘極介電層96的厚度較佳在大約1 nm至大約6 nm間。
鰭式場效電晶體(FinFET)106的閘極102、104藉由填塞在介電層86上的凹陷82部份而形成，係以適當閘極導體材料沉積層，並使用習知平坦化製程例如化學機械研磨(CMP)研磨至 平面MOSFET區域42，以建立平坦表面26。這是熟習此技藝者熟知的技術，亦即鑲嵌製程。閘極導體材料包含如鎢的反射金屬、摻雜或未摻雜的多晶矽、如矽化鎳或矽化鎢的金屬矽化物或者這些材料的組合。閘極102、104的類型建構功函數，以致於影響鰭式場效電晶體(FinFET)106的臨限電壓(Vt)。藉由習知微影與蝕刻製程，相對於氧化帽蓋28與平面MOSFET區域42具有選擇性，隨後圖案化閘極導體材料，以界定閘極102、104。藉由絕緣蓋28材料與半導體鰭30材料，半導體鰭30的閘極102、104彼此分隔。因此，相對的閘極102、104於分裂閘極型式中並不電性連接，其中各閘極102、104分別偏壓以控制鰭式場效電晶體(FinFET)106。
目前導入源極-汲極摻雜至暴露的源極與汲極區域32、34的側壁，而且以習知方式例如氣相摻雜或離子植入製程進行。氧化物帽蓋28與閘極102、104保護鰭式場效電晶體(FinFET)106的通道區域88避免受到源極-汲極摻雜製程的污染。先前藉由通道摻雜製程導入至源極與汲極區域32、34的通道摻雜，由源極-汲極較高濃度摻雜量有效地掩蓋。源極與汲極區域32、34的摻雜過程通常需要使用數個遮罩，例如光阻遮罩以導入多種濃度的不同摻雜質而形成P型通道FinFET與N型通道FinFET。
參閱圖20A與20B，其中相似元件符號指向圖19A與19B的相似元件，而且在隨後製造步驟中，絕緣層108較佳是一種軟且可流動以及容易平坦化的氧化物，例如硼磷矽酸鹽玻璃(BPSG)、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)或四乙基 正矽酸鹽(TEOS)，而且沉積絕緣層108以及藉由習知平坦化製程例如化學機械研磨(CMP)製程以達到平坦表面26，且平坦表面26與氧化物帽蓋28及平面半導體裝置42的頂部水平表面一致。絕緣層108的其餘部分填塞環繞平面半導體裝置42與鰭式場效電晶體(FinFET)106的空隙區域。完成的半導體結構包含平面半導體裝置42與鰭式場效電晶體(FinFET)106，而且可有許多此種結合的半導體結構重複在基板10表面，以準備進行習知製程，可包含形成接觸介層/柱體、多層圖案金屬化以及層間介電層。
因為鰭式場效電晶體(FinFET)106的通道寬度係垂直的，所以鰭式場效電晶體(FinFET)106的通道寬度是與鰭30的高度成比例。因此，通道寬度大約等於閘極介電層96所覆蓋的半導體鰭30之高度，且與閘極102、104分隔。因為用於形成介電層86的製造技術，鰭式場效電晶體(FinFET)106的通道寬度大於鰭式場效電晶體(FinFET)72(圖14A,14B)的通道寬度，這對於半導體結構的特定應用是有益處的。
於此之參考名詞例如“垂直的”、“水平的”等應該以範例方式解釋，而不是用來限制，以建立參考座標。名詞“水平的”於此是定義為與習知平面或者基板10的表面15或習知表面平行的平面，而不論基板10的實際空間方位。名詞“垂直的”表示垂直於先前定義之水平方向的方向。名詞例如“在上(on)”、“上方(above)”、“下方(below)”、“側(如側壁)”、“較高”、“較低”、”於...之上”、”以下”“低於”等是相對於水平表面。其他的參考方式可使用於描述本發明，而不偏離本發明得精神與範疇。
製造半導體結構藉由特定順序的製造階段與步驟描述。然而，應該明瞭此特定順序可加以變動。例如，兩個或多個製造階段的順序可相對於目前順序切換。再者，兩個或多個製造階段可同時或部份同時操作。其次，可省略不同製造步驟而且可增加其他製造步驟。應該明瞭所有變化皆在本發明的範圍內。也應該明瞭本發明的特色未必按照比例顯示於圖式中。
本發明已藉由實施例加以描述，熟習此技藝者應該瞭解本發明可在附屬申請專利範圍的精神與範圍內的改良情形下實施。因此，本發明實施例不限定於已描述與已說明的明確形式，然而用於包含所有改良將不偏離本發明的精神與範疇。
10‧‧‧單晶塊基板
12‧‧‧墊氧化層
14‧‧‧墊氮化層
15‧‧‧暴露表面
16‧‧‧溝槽
17‧‧‧側壁
18‧‧‧磊晶層
20‧‧‧含氧離子
22‧‧‧氧濃度分佈
24‧‧‧埋‧‧‧式隔離區域
26‧‧‧平坦表面
28‧‧‧保護絕緣蓋
30‧‧‧半導體鰭
32‧‧‧源極區域
34‧‧‧汲極區域
36‧‧‧淺溝槽隔離區域
38‧‧‧阻擋遮罩
40‧‧‧凹陷區域
42‧‧‧平面半導體裝置
44‧‧‧閘電極
46‧‧‧薄閘極介電層
48‧‧‧側壁間隙壁
50‧‧‧源極
52‧‧‧汲極
54‧‧‧通道
56‧‧‧絕緣層
58‧‧‧閘極溝槽
60‧‧‧垂直側壁
62‧‧‧垂直側壁
64‧‧‧通道區域
66‧‧‧閘極介電層
68‧‧‧閘極
69‧‧‧閘極
70‧‧‧間隙壁
72‧‧‧鰭式場效電晶體(FinFET)
74‧‧‧絕緣填塞料
80‧‧‧側壁間隙壁
82‧‧‧凹陷
86‧‧‧介電層
88‧‧‧通道區域
96‧‧‧閘極介電層
98‧‧‧垂直側壁
100‧‧‧垂直側壁
100‧‧‧閘極
102‧‧‧閘極
106‧‧‧鰭式場效電晶體(FinFET)
108‧‧‧絕緣層
所附圖式於此作為本發明說明書之一部份，配合本發明內容，以及實施例之詳細說明描述本發明實施例，以解釋本發明的原理概念。
圖1-14是本發明實施例在不同製造階段的一部份基板之示意圖，其中A代表俯視圖而B通常為A圖中沿著線B-B擷取之相對應截面圖；以及圖15-20是本發明另一實施例在不同製造階段的一部份基板之示意圖，其中A代表俯視圖而B通常為A圖中沿著線B-B擷取之相對應截面圖。
10‧‧‧基板
12‧‧‧墊氧化層
18‧‧‧磊晶層
24‧‧‧埋式隔離區域
26‧‧‧平坦表面
28‧‧‧保護絕緣蓋
36‧‧‧淺溝槽隔離區域
42‧‧‧平面半導體裝置
44‧‧‧閘電極
46‧‧‧薄閘極介電層
48‧‧‧側壁間隙壁
50‧‧‧源極
52‧‧‧汲極
54‧‧‧通道
56‧‧‧絕緣層
60‧‧‧垂直側壁
62‧‧‧垂直側壁
66‧‧‧閘極介電層
68‧‧‧閘極
69‧‧‧閘極
70‧‧‧間隙壁
72‧‧‧鰭式場效電晶體
74‧‧‧絕緣填塞料

Claims (17)

  1. 一種製造半導體結構之方法，包含：於一基板上之一遮罩中，蝕刻一第一溝槽；形成一半導體鰭於第一溝槽中，該半導體鰭具有一通道區域；在部份形成該半導體鰭後，形成一隔離區域於該半導體鰭與該基板間；形成一閘極結構，與該半導體鰭的該通道區域相交；以及當形成該閘極結構時，以該遮罩支撐該半導體鰭。
  2. 如申請專利範圍第1項所述之方法，其中形成該半導體鰭之該步驟更包含：實施選擇性磊晶成長製程，以在水平表面上相較於在垂直表面上具有較大成長速率之方式，沉積構成該半導體鰭的一半導體。
  3. 如申請專利範圍第1項所述之方法，其中形成閘極結構的該步驟更包含：在該基板上於該遮罩中蝕刻一第二溝槽，該第二溝槽暴露出該通道區域；以及形成該閘極結構於該第二溝槽。
  4. 如申請專利範圍第3項所述之方法，更包含：摻雜該暴露出的通道區域；以及當摻雜該暴露出的通道區域時，以該遮罩支撐該半導體鰭。
  5. 如申請專利範圍第3項所述之方法，其中形成閘極結構的該步驟更包含：形成一第一閘極於該第二溝槽的一第一部份，側接該通道區域之一第一側壁；以及形成一第二閘極於該第二溝槽之一第二部份，側接該通道區域之一第二側壁，該第一閘極與第二閘極電性隔離。
  6. 如申請專利範圍第5項所述之方法，更包含：在形成該第一閘極前，形成一第一閘極介電層於該第一側壁上；以及在形成該第二閘極前，形成一第二閘極介電層於該第二側壁上。
  7. 如申請專利範圍第1項所述之方法，其中該閘極結構是藉由鑲嵌製程形成。
  8. 如申請專利範圍第1項所述之方法，其中該半導體鰭是藉由鑲嵌製程形成。
  9. 如申請專利範圍第1項所述之方法，更包含：形成一平面裝置鄰近該半導體鰭。
  10. 如申請專利範圍第9項所述之方法，其中該平面裝置是金氧半導體場效電晶體。
  11. 一種製造一半導體結構之方法，包含：於覆蓋一基板的一遮罩中，蝕刻一溝槽； 形成一第一磊晶層於該溝槽中；經由該遮罩，植入離子入該第一磊晶層，使得該溝槽將該植入離子與該第一磊晶層自我對準；將該植入離子轉換成一埋式隔離區域，以電性隔離該第一磊晶層與該基板；以及形成一第二磊晶層於該溝槽中且在該第一磊晶層上。
  12. 如申請專利範圍第11項所述之方法，其中該第一磊晶層與該基板包含矽，且埋式隔離區域包含氧與矽，且植入離子入該第一磊晶層的步驟更包含：植入含氧離子入該第一磊晶層。
  13. 如申請專利範圍第11項所述之方法，其中定義一介面係介於該第一磊晶層與該基板間，且植入離子入該第一磊晶層的步驟更包含：選擇一離子能量，使得離子分佈範圍是接近該介面。
  14. 如申請專利範圍第11項所述之方法，其中該基板為單晶而該溝槽延伸至該基板，且形成該第一磊晶層的步驟更包含：使用該基板作為形成該第一磊晶層之晶種。
  15. 如申請專利範圍第11項所述之方法，其中形成第二磊晶層的步驟更包含：使用該第一磊晶層作為形成該第二磊晶層之晶 種。
  16. 如申請專利範圍第11項所述之方法，其中該植入離子藉由熱處理轉換成該埋式隔離區域。
  17. 如申請專利範圍第16項所述之方法，其中該熱處理退火該第一磊晶層因離子植入造成的損害，且更包含：使用該第一磊晶層作為形成該第二磊晶層的晶種。
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