CN111029251A - 一种用于形成半导体器件的栅极的方法 - Google Patents
一种用于形成半导体器件的栅极的方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- LNDHQUDDOUZKQV-UHFFFAOYSA-J molybdenum tetrafluoride Chemical compound F[Mo](F)(F)F LNDHQUDDOUZKQV-UHFFFAOYSA-J 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 230000003746 surface roughness Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910010038 TiAl Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910003986 SicO Inorganic materials 0.000 description 1
- 229910034327 TiC Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
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Abstract
根据本发明构思的一方面,提供了一种用于形成半导体器件的栅极的方法,该方法包括:提供半导体结构,所述半导体结构包括基板和在所述基板上方突出的沟道结构,在沟道结构上形成栅极介电层,在栅极介电层上形成栅极功函数金属层,沉积硅的牺牲材料以形成初步牺牲栅极填充结构,所述初步牺牲栅极填充结构覆盖所述功函数金属并且在所述基板上方突出达初始高度,回蚀所述初步牺牲栅极填充结构的上表面以获得在所述基板上方的高度减小了的最终牺牲栅极填充结构,以及通过转化反应用导电栅极填充材料代替所述最终牺牲栅极填充结构的牺牲材料,由此形成用于所述沟道结构的栅电极。
Description
技术领域
本发明构思涉及一种用于形成半导体器件的栅极的方法。
背景技术
垂直场效应晶体管(VFET)是一种其中沟道与基板成法向地定向的场效应晶体管。由于垂直定向的沟道结构,栅极长度不由线宽而是由栅极导体层的厚度来限定。其次,垂直晶体管器件的源极和漏极区相对于彼此垂直放置。出于这些原因,垂直晶体管器件尤其能够使每单位面积形成相当多的数目的FET。
图1a-c示意性地描绘了用于中间VFET器件结构1的常规栅极形成办法。图1a示出了基板3和数个垂直沟道结构5。沟道结构5的下部可以被嵌入在绝缘层7中。在栅极形成期间,垂直沟道结构5可以被栅极电介质和功函数栅极金属(共同被标记为6)覆盖。栅极形成可以进一步包括沉积导电栅极填充层8,使得其覆盖并围绕垂直沟道5。然后通过回蚀填充层8以形成仅围绕每个沟道5的一部分的厚度减小的导电材料层9来限定栅极长度。通常,钨(W)由于其良好的导电和填充属性而被用于填充层8。
类似的钨回蚀工艺同样可以在水平沟道器件的栅极形成(诸如鳍式FET的栅极形成)期间被执行。继在栅极沟槽中沉积一个或多个功函数金属层之后,钨可以被沉积以填充栅极沟槽中的剩余空间,并且之后在栅极沟槽中被回蚀到期望的水平。
发明内容
发明人已经认识到涉及导电层回蚀(例如钨层)的上述现有技术栅极形成方法可能导致栅极电极呈现出成问题的程度的表面粗糙度。表面粗糙度可能致使对栅极长度的控制是困难的。表面粗糙度可进一步导致栅电极和顶电极之间随后形成的隔离层的变化的厚度和粗糙度。本发明构思的目的因而是提供一种减轻或至少减少上面提到的问题的用于形成半导体器件的栅极的方法。从下面可以理解其他和/或替代目的。
根据本发明构思的一方面,提供了一种用于形成半导体器件的栅极的方法,该方法包括:
提供半导体结构,其包括基板和在基板上方突出的沟道结构,
在沟道结构上形成栅极介电层,
在栅极介电层上形成栅极功函数金属层,
沉积硅的牺牲材料以形成初步牺牲栅极填充结构,该初步牺牲栅极填充结构覆盖功函数金属并且在基板上方突出达初始高度,
回蚀初步牺牲栅极填充结构的上表面以获得在基板上方高度减小了的最终牺牲栅极填充结构,以及
通过转化反应用导电栅极填充材料代替最终牺牲栅极填充结构的牺牲材料,由此形成用于沟道结构的栅电极。
通过本发明的方法,用于半导体器件的栅电极可以被形成为具有光滑的上表面。这是通过硅初步牺牲栅极填充结构的回蚀和最终牺牲栅极结构向导电栅极填充结构的转化的组合来实现的。
在栅极填充层的回蚀之后可能导致的表面粗糙度(如在现有技术中)可归因于通常被用于栅极填充的导电材料的相当大的晶粒大小(特别是W)。硅的回蚀,特别是非晶硅或多晶硅的回蚀,不会导致相同程度的表面粗糙度。因此,硅初步牺牲栅极填充结构的回蚀允许形成具有光滑上表面的最终牺牲栅极结构。转化反应可接着导致最终牺牲栅极结构的原子被导电栅极填充材料的原子代替。由此,具有相应光滑的上表面的导电栅极填充结构可以被获得。同时,栅极介电层和功函数金属在沟道结构上的存在可以抵消在回蚀期间对沟道结构的蚀刻。
初步牺牲栅极可以被形成为至少部分地嵌入沟道结构的至少一个沟道区域。最终栅电极可因而围绕沟道结构的沟道区域。这进而允许栅电极提供良好的静电控制。
该方法可以进一步包括在形成栅极介电层和栅极功函数金属层之前在基板(即,其上表面)上形成绝缘层。
这样,栅电极可以通过绝缘层与基板隔离,该绝缘层可以形成底部介电层。同样,绝缘层可以在牺牲材料沉积和转化反应期间根据工艺条件提供对基板的进一步掩蔽。
栅极介电层和功函数金属层可以被沉积在沟道结构上和绝缘层的上表面上。因此,栅极介电层和功函数金属层可以被沉积以覆盖沟道结构和绝缘层的上表面两者。栅极介电层和栅极功函数金属层可以被形成为覆盖沟道结构的至少一个沟道区域。
该方法可以进一步包括在其回蚀之前平坦化经沉积的牺牲材料以形成具有经平坦化的上表面的初步牺牲栅极填充结构。这可以促成在回蚀之后获得具有均匀高度/厚度的最终牺牲栅极填充结构。
用导电栅极填充材料替换最终牺牲栅极填充结构的牺牲材料可以包括完全地替换最终牺牲栅极填充结构的牺牲材料。
栅电极可因此被形成为不带有残留在导电填充栅极结构中的牺牲材料的痕迹。换言之,最终牺牲栅极填充结构可以被导电栅极填充结构完全替代/被转换成导电栅极填充结构。
牺牲材料可以包括非晶硅(a-Si)或多晶硅。可以使用常规的沉积技术(诸如化学气相沉积(CVD))以廉价且高效的方式无针孔地(free of pin-hole)沉积这些材料。
导电材料可以包括钨或钼。硅材料(诸如a-Si和多晶硅)可以容易地借助于转化反应被转换成钨或钼。而且,钨和钼都能够形成具有良好电气属性的栅电极。
用导电材料代替牺牲材料可以包括将牺牲材料暴露于氟化钨气体(诸如六氟化钨)或氟化钼气体。牺牲材料可因而与氟化钨气体反应且被钨替代。替代地,牺牲材料可以与氟化钼气体反应且被钼代替。
本发明的方法适用于垂直和水平沟道器件两者的栅极形成。垂直沟道器件可以是具有环绕栅(GAA)配置(即,栅电极在圆周方向上完全包围垂直沟道结构)的垂直场效应晶体管(VFET)。水平沟道器件可以是鳍式FET(例如,具有三栅极配置)或具有GAA配置的水平纳米线FET(NW-FET)。
其中沟道结构被垂直地定向的实施例允许形成具有垂直沟道(诸如垂直场效应晶体管)且栅极具有光滑上表面的半导体器件。
牺牲材料可以被沉积以完全地覆盖被垂直地定向的沟道结构。之后可以通过沿着垂直沟道结构将初步牺牲栅极填充结构回蚀到期望水平来限定栅极长度。
初步牺牲栅极填充结构可以被回蚀,以使得沟道结构在最终牺牲栅极填充结构上方突出。
因而,最终牺牲栅极填充结构(以及相应地还有导电栅极填充结构)可以被定义为沿着沟道结构的垂直部分延伸。在牺牲栅电极填充结构上方突出的沟道结构的一部分可促成随后的源/漏区和源/漏电极形成。
该方法可以进一步包括,继替换牺牲材料之后,从沟道结构的在最终牺牲栅极填充结构上方突出的部分中移除栅极介电层和功函数金属层。最终牺牲栅极填充结构上方的沟道结构的该部分可因此被暴露以用于后续处理,诸如源/漏区和源/漏电极形成。
附图说明
参考附图,通过以下解说性和非限制性详细描述,将更好地理解本发明构思的以上以及附加目标、特征和优点。在附图中,除非另有说明,否则相同的附图标记将被用于相同要素。
图1a-c示意性地解说了用于VFET的常规栅极形成办法。
图2a-e示意性地解说了用于形成具有被垂直地定向的沟道结构的半导体器件的栅极的方法。
图3示意性地解说了用于形成具有被水平地定向的沟道结构的半导体器件的栅极的方法。
具体实施方式
现在将参考图2a至2e公开一种用于形成半导体器件的栅极的方法。应当注意,由于附图的示意性性质,各种结构和层的相对尺寸未按比例绘制。相反,尺寸已被调适以便于图示清楚和促进对以下描述的理解。
在图2a所示的方法的阶段,半导体结构1已被提供。半导体结构1包括基板3。基板可以是常规类型的半导体基板,诸如Si基板。其他示例可以是Ge基板、SiGe基板、SiC基板、SOI基板、GeOI基板或SiGeOI基板。
半导体结构1包括沟道结构5。沟道结构5在基板3上方突出。沟道结构5被垂直地定向,即平行于基板3的法线方向延伸。下面将参考单个沟道结构5,但是如从图中可以看出的,半导体结构1可以包括数个类似的沟道结构5。沟道结构5可以沿着基板3以规则的阵列(例如包括多个行和列)来被布置。
沟道结构5可以由一种或多种半导体材料制成,例如Si、SiGe或Ge。如本领域中已知的,沟道结构5中的每个沟道结构可以被形成在基板3的经掺杂的底部电极区域上,使得较低的源/漏区可以被形成在每个沟道结构5的下方。沟道结构5可被以常规方式形成,例如通过图案化被形成在基板3上的一个或多个外延半导体层。作为一些非限制性示例,可以在Si层、SiGe层或Ge层中,或者在层堆叠(诸如SiGe/Si/SiGe层堆叠或SiGe/Ge/SiGe层堆叠)中图案化沟道结构5。本发明的方法适用于结较少(junction less)的器件以及反转模式器件,并且可以相应地掺杂(诸)层。沟道结构5可以被图案化以呈现例如圆形、椭圆形或矩形的截面形状并因而形成柱状或纳米线状的结构。沟道结构5的图案化可以包括在一个或多个外延半导体层上限定经图案化的掩模(诸如(例如,Si3N4、旋涂碳(spin-on-carbon)或碳基图案化膜的)硬掩模)、基于氧化物的掩模或光致抗蚀剂掩模,以及在将经图案化的掩模用作蚀刻掩模时蚀刻该一个或多个外延半导体层。如图2a所示,掩膜可以继沟道图案化之后被移除。然而,还可以将经图案化掩模的掩模部分保持在经图案化的沟道结构的顶部上,直到继栅极形成之后的上部源极/漏极处理为止。
绝缘层7已被形成在基板1上。绝缘层7覆盖基板3的上表面,更具体地说,基板3的(诸)底部电极区域。绝缘层7围绕沟道结构5的下部。更具体而言,绝缘层7可以完全地包裹在沟道结构5的下部周围。可以通过沉积绝缘材料以覆盖基板1的上表面和沟道结构5来形成绝缘层7。在对经沉积的绝缘材料进行平坦化(例如通过CMP)之后,可以执行回蚀以形成具有期望厚度的绝缘层7。绝缘层7可以由经CVD沉积的介电材料形成,例如氮化硅Si3N4或氧化物材料(诸如SiO2、SiCo、SiON或SiOCN)。
继形成绝缘层7之后,共形栅极介电层和功函数金属(WFM)层(共同被标记为层6)的堆叠可以被形成在沟道结构5上。栅极介电层可以由一层或多层常规栅极介电材料(诸如SiO2或HfOx)或任何其他合适的高k栅极介电材料形成。从图中可以看出,栅极介电层可以被沉积以覆盖沟道结构5的侧壁。栅极介电层可以进一步覆盖沟道结构5的上表面(或者掩模部分,如果在沟道结构图案化之后仍然保留的话)。栅极介电层可被沉积以同样覆盖绝缘层7。可以通过原子层沉积(ALD)来沉积栅极介电层。
功函数金属层可以被形成为完全地覆盖栅极介电层。功函数金属层可以由有效功函数金属(EWF)形成。取决于要形成的垂直沟道器件的导电性类型,导电层可以例如由一种或多种p型EWF金属(诸如TiN、TaN、TiTaN)或者由一种或多种n型EWF金属(诸如Al、TiAl、TiC或TiAlC)或复合层(诸如TiN/TiAl或TiN/TaN/TiAl)形成。WFM层可以例如通过ALD被沉积为共形层。
在图2b所示的方法的阶段,牺牲材料已被沉积在半导体结构1上。经沉积的牺牲材料完全地覆盖沟道结构5。如图2b中示意性地指示的,经沉积的牺牲物可以(例如,通过CMP)被平坦化以形成具有平坦上表面的初步牺牲栅极填充结构10。初步牺牲栅极填充结构10的上表面可以至少基本上与覆盖沟道结构5的上表面的层部分6齐平。当覆盖沟道结构5的上表面的层部分6被暴露时,平坦化可被停止。替代地,如果来自沟道结构图案化的掩模部分保留在沟道结构5上,则初步牺牲栅极填充结构10的上表面可以至少基本上与掩模部分的上表面齐平。在该情形中,当掩模部分的上表面被暴露时,平坦化可被停止。初步填充结构10嵌入并包裹在沟道结构5周围。初步填充结构10在基板3上方突出达初始高度Hi。初步牺牲结构10覆盖栅极电介质和WFM层堆叠6。初步填充结构10完全地嵌入沟道结构5的沟道区域。牺牲材料可以是非晶硅。替代地,牺牲材料可以是多晶硅。牺牲材料可以通过CVD或溅射来被沉积。
在图2c所示的方法的阶段,初步牺牲栅极填充结构10已被回蚀以形成最终牺牲栅极填充结构11。沟道结构5在最终牺牲栅极填充结构11上方突出。初步牺牲栅极填充结构10已被回蚀,以使得最终牺牲栅极填充结构11在基板3上方具有减小的高度Hr。例如,各向同性干法蚀刻工艺可被用于回蚀,诸如使用基于氟的蚀刻剂(诸如SF6)的反应离子蚀刻(RIE)。
在图2d中所示的方法的阶段,最终牺牲栅极填充结构11的牺牲材料已经被导电栅极填充材料代替,由此形成包裹在沟道结构5周围的导电栅极填充结构12。导电栅极填充结构12和WFM层可以一起形成用于沟道结构5的最终围裹式(wrap-around)栅电极。牺牲材料已通过转化反应被替换。通过用导电栅极填充材料的原子替换牺牲材料的原子,转化反应用导电栅极填充材料替换了最终牺牲栅极填充结构11的牺牲材料。转化反应可以被执行以使得最终牺牲栅极填充结构11的牺牲材料被导电栅极填充材料完全地替代。
转化反应可以包括将最终牺牲栅极填充结构11的牺牲材料暴露于将导电栅极填充材料包括作为成分的反应气体。反应气体可以是六氟化钨WF6。由此,可以通过转化反应2WF6+3Si-->2W+3SiF4形成W栅极填充结构。可以将反应气体供应到其中布置有结构1的反应器腔室中。附加气体可以被供应到反应器腔室中,诸如(惰性)载气,例如氩气或氮气。转化反应可以在约300至450℃(反应器腔室的环境温度)范围内的温度下被执行。压力可为1托左右。其他转化反应也是可能的,例如使用氟化钼MFx作为反应气体。由此,可以通过相应的转化反应形成Mo栅极填充结构,其中牺牲材料的Si充当还原剂。
在任何情形中,转化反应可以在足够长的时间下被执行,以使最终牺牲栅极填充结构13的牺牲材料被导电栅极填充材料完全地替代。
在图2e所示的方法的阶段,栅极介电层和功函数金属层6已经从沟道结构5的在栅极填充结构12上方突出的部分中被移除。即,从最终牺牲栅极填充结构12上方的沟道结构5的区域。可以在用于对钨和沟道结构5的材料选择性地蚀刻栅极介电层和功函数金属层6的蚀刻过程中移除栅极介电层和功函数金属层6。例如,包括BCl3/Cl2蚀刻化学物质的各向同性蚀刻过程可以被使用。
该方法之后可以通过沉积(例如,SiO2或一些其他低k电介质的)另一绝缘层来进行,该绝缘层嵌入(诸)栅电极和(诸)沟道结构的(先前)暴露的突出部分。该方法之后可以通过使用本领域中本身已知的技术形成上部源/漏区、源/漏电极和接触形成来进行。
在上文中,已经在先栅极(gate first)工艺(即,栅极形成在顶部源极/漏极和电极形成之前)的上下文中描述了该方法。然而,该方法也与后栅极/替代金属栅极(RMG)工艺兼容。如本领域技术人员所知,在常规的RMG工艺中,可以在顶部源极/漏极和电极形成之后从栅极沟槽中移除a-Si或多晶硅虚设栅极。一种或多种栅极金属此后可被沉积在沟槽中,包括钨栅极填充金属,其随后可被回蚀至期望的高度/厚度。如上面描述的,该回蚀可导致表面粗糙。本发明的方法可改为按以下方式通过替换常规的钨填充沉积和回蚀(在虚设栅极移除之后)而在RMG工艺中被实现:在栅极沟槽中形成牺牲硅材料的初步牺牲栅极填充结构,将初步牺牲栅极填充结构回蚀至期望的高度,并且之后执行转化反应以在栅极沟槽中形成导电栅极填充结构。
在图2a至2e中,已经针对包括被垂直地定向的沟道结构的半导体结构实现了该方法。然而,也可以针对其中沟道结构被水平地定向的半导体结构来实现该方法。图3中示出了一种结构,其包括数个(即,一个或多个)被水平地定向的沟道结构15。所解说的沟道结构15采取水平纳米线的形式,但是鳍形半导体结构也是可能的。在垂直于沟道结构15的水平方向截取的截面中示出了处于栅极沟槽16内的某位置处的该结构。可以通过移除被嵌入在绝缘层17中的虚设栅极来形成栅极沟槽16。(例如a-Si或多晶硅的)牺牲材料已被沉积在栅极沟槽16中,以嵌入沟道结构15的延伸穿过栅极沟槽16、因而跨沟道结构的水平方向延伸的各部分。牺牲材料的沉积可以随栅极介电层和WFM层在沟道结构上的沉积进行。如图3中示意性地指示的,经沉积的牺牲物可以(例如,通过CMP)被平坦化以形成具有平坦上表面的初步牺牲栅极填充结构14。初步牺牲栅极填充结构14可随后被回蚀,以在栅极沟槽16内形成期望的减小了的高度的最终牺牲栅极填充结构。最终牺牲栅极填充结构可经受如上面描述的转化反应,以形成(例如,W或Mo的)导电栅极填充结构。导电栅极填充结构和WFM层可以一起形成用于一个或多个沟道结构15的最终围裹式栅电极。
在上文中已主要参考有限数量的示例描述了本发明的构思。然而,如本领域技术人员容易领会的,除了上文所公开的各示例以外的其他示例在如所附权利要求限定的本发明的构思的范围内同样是可能的。
Claims (14)
1.一种用于形成半导体器件的栅极的方法,所述方法包括:
提供半导体结构,所述半导体结构包括基板和在所述基板上方突出的沟道结构,
在所述沟道结构的表面上形成栅极介电层,
在所述栅极介电层的表面上形成栅极功函数金属层,
沉积硅的牺牲材料以形成初步牺牲栅极填充结构,所述初步牺牲栅极填充结构覆盖所述功函数金属并且在所述基板上方突出达初始高度,
回蚀所述初步牺牲栅极填充结构的上表面以获得在所述基板上方的高度减小了的最终牺牲栅极填充结构,以及
通过转化反应用导电栅极填充材料代替所述最终牺牲栅极填充结构的牺牲材料,由此形成用于所述沟道结构的栅电极。
2.根据权利要求1所述的方法,其特征在于,所述初步牺牲栅极被形成为嵌入所述沟道结构的至少一个沟道区域。
3.根据任一前述权利要求所述的方法,其特征在于,进一步包括在形成所述栅极介电层和所述栅极功函数金属层之前,在所述基板上形成绝缘层。
4.根据权利要求3所述的方法,其特征在于,所述栅极介电层和所述功函数金属层被沉积在所述沟道结构上和所述绝缘层的上表面上。
5.根据任一前述权利要求所述的方法,其特征在于,进一步包括在其回蚀之前平坦化经沉积的牺牲材料以形成具有经平坦化的上表面的所述初步牺牲栅极填充结构。
6.根据任一前述权利要求所述的方法,其特征在于,用导电栅极填充材料替换所述最终牺牲栅极填充结构的牺牲材料完全地替换了所述最终牺牲栅极填充结构的牺牲材料。
7.根据任一前述权利要求所述的方法,其特征在于,所述牺牲材料包括非晶硅或多晶硅。
8.根据任一前述权利要求所述的方法,其特征在于,所述导电材料包括钨或钼。
9.根据任一前述权利要求所述的方法,其特征在于,用所述导电材料代替所述牺牲材料包括将所述牺牲材料暴露于氟化钨气体或氟化钼气体。
10.根据任一前述权利要求所述的方法,其特征在于,所述沟道结构被垂直地定向。
11.根据权利要求10所述的方法,其特征在于,所述牺牲材料被沉积以完全地覆盖所述沟道结构。
12.根据权利要求10和11中任一项所述的方法,其特征在于,所述初步牺牲栅极填充结构被回蚀,以使得所述沟道结构在所述最终牺牲栅极填充结构上方突出。
13.根据权利要求11到12中任一项所述的方法,其特征在于,进一步包括,继替换所述牺牲材料之后,从所述沟道结构的在所述最终牺牲栅极填充结构上方突出的部分中移除所述栅极介电层和所述功函数金属层。
14.根据权利要求1到9中任一项所述的方法,其特征在于,所述沟道结构被水平地定向。
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