TWI338328B - Dual silicon layer for chemical mechanical polishing planarization - Google Patents

Dual silicon layer for chemical mechanical polishing planarization Download PDF

Info

Publication number
TWI338328B
TWI338328B TW093116645A TW93116645A TWI338328B TW I338328 B TWI338328 B TW I338328B TW 093116645 A TW093116645 A TW 093116645A TW 93116645 A TW93116645 A TW 93116645A TW I338328 B TWI338328 B TW I338328B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor device
fin
planarization
gate
Prior art date
Application number
TW093116645A
Other languages
English (en)
Other versions
TW200503095A (en
Inventor
Krishnashree Achuthan
Shibly S Ahmed
Haihong Wang
Bin Yu
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200503095A publication Critical patent/TW200503095A/zh
Application granted granted Critical
Publication of TWI338328B publication Critical patent/TWI338328B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1338328 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置及其製造方法。本發明對-於雙閘極裝置（double gate devices)具有特別之適用性。 【先前技術】 由於對超大尺寸積體半導體裝置相關之高密度及性 能需求的逐漸提昇’故須要求半導體裝置之設計特徵 (design features) ’如雙閘極長度於ι〇〇奈米（nm)以下、高 可靠性以及提高製造產量。將設計特徵縮小於】〇〇奈米以 下將挑戰傳統方法之極限。 例如’當傳統平面型金屬氧化物半導體場效電晶體 (MOSFETs)之閘極長度在1〇〇奈米以下時，則與短通道效 應有關之問題，例如源極與汲極間之過量漏電流，將變得 越來越難克服。此外，電子移動速度（m〇bility)的降低以及 製程上的問題亦造成傳統MOSFETs難以依比例縮小至包 含逐漸減小之裝置特徵。因此將探究新的裝置結構以改善 FET性能並容許裝置更進一步地縮小。 。 雙閘極MOSFETs代表被視為可接替現存平面型 ▲ SFETs之新結構之選擇。在某些方面，雙問極M〇spE丁s 較傳統整塊石夕元件（bu】k si丨ic〇n)M〇SFETs提供更佳特性。 這些改善的產生係因為雙閘極·阳於通道的兩側均 具有閉電極’而不似傳統MOSFETs僅於單側上具有間電 極°當存在兩個間電極時’藉由汲極產生之電場可經由通 C之源極μ作佳麵n兩個閘極可控制大約兩倍 92634 5 " 於單閘極所控制之電流，因而導致較強之交換訊號 * (switching signal)。 鰭狀場效電晶體（FinFET)係一種近來之雙閘極結構， 其顯現良好的短通道性能。FinFET包含一個形成於垂直鰭 (vertical fin)内之通道。FinFET結構係使用相似於傳統平 面型MOSFETs所用之佈局（lay out)及製程技術所製造。 【發明内容】 ψ- 與本發明一致之一實施例提供了一種雙閘極 MOSFET，其於閘極區上方具有雙重多晶矽層以使用於提 尚多晶矽之化學機械研磨（chemicai mechanicai p〇】ishing， CMP)平面化。 與本發明一致之一實施例提供了一種製造半導體裝 置之方法。t亥方法包括於絕緣體上形成轉結構並於至少一 部份之韓結構以及一部份之絕緣體的上方形成問極結構。 該閘極結構包括第一層以及形成於第一層上方之第二層。 該方法進—步包括藉由㈣極結構進行化學機械研磨曰 (CMP)而將該閉極結構平面化。閉極結構第— 速率可能較問極結構第二層之平面化速率慢^亥平面化過 程會持續直至第-層曝露於結構上方之區域内。 〃'本毛明一致之另一實施例係針對半 “ 置包括形成於絕緣體上方之鰭結構“亥：：。該裝 第二端。於半導體裝置中 二…。。括第-及 道。將非晶石夕層形成於至少一；份=韓結構係做為通 層則形成於至少一部份之非 …‘構上方。多晶矽 非曰曰矽層周圍。該非晶矽層突出 92634 6 1338328 l k.鳍、’、。構上方區域中之多晶石夕層。源極區域連接於鰭結 構之第一端。汲極區域連接於鰭結構之第二端。 【實施方式】 本兔月之下列詳細敘述請參照附圖。於不同圖形中所 使用之相同參考編號係用以定義相同或相似元件。此外， 下列之詳細敘述並不限制本發明。反之，本發明之領域範 圍係藉由附加之申請專利範圍及同等物所界定。 於此所使用之FinFET —詞係指M0SFET之一種型 式，其中，導電通路（conductingchannel)係形成於垂直之 矽鰭’’（fin)内。FinFETs為該技術領域所眾所周知。 第1圖表示依據本發明之具體實施例所形成之半導體 裝置100的橫戴面圖。參照第1圖，半導體裝置1〇〇包括 一種絕緣層上覆石夕（silicon on insulator，SOI)之結構，該結 構包括矽基材110、埋藏氧化層120(buried〇xidelayer)以 及形成於埋藏氧化層120上方之矽層〗3〇。埋藏氧化層12〇 及石夕層130可經由傳統方法形成於基材】】〇上。 於一實施例中，埋藏氧化層12〇可包含二氧化矽且其 厚度範圍大約為]000A至3000A。矽層13〇可包含單晶或 多晶矽。矽層1 30係使用於形成雙閘極電晶體之鰭結構， 以下將有更詳盡之描述。 於另一個與本發明一致之實施例中，基材11〇與層13〇 可包含其他半導體材料，如鍺，或半導體材料之組合，如 矽-鍺。埋藏氧化層120亦可包含其他介電材料。 介電層140，例如氮化矽層或氧化矽層（例如，二氧化 92634 7 石夕叫），得、形成於石夕層13〇上方，以於隨後之_ 期間做為保護罩。於一示範之實施例中，介電層】40可長 成之厚度範圍大約為15从至編。然後，光阻材料 (Photoresist material)可經沉積並經圖案化以形成光阻光罩 150 (Ph_resist mask)而供隨後製程使用。光阻可經由任何 ^統方法》儿積並圖案化（patterned)。 接著將半導體裝置100蝕刻並移除光阻光罩15〇。於 ^不範之實施例中，㈣13()可經由傳統方法㈣並使钱 :於埋臧氧化層120終止以形成轉。於鰭形成後，可在鄰 近於鰭之各別端點形成源極和㈣區域。例如，於一 施例中，可以傳統方法沉積、圖案化並㈣石夕層、 鍺層或矽及鍺之組合層以形成源極和汲極區域。於另“ 可經由沉積肠财層⑽以同時形成源極、二 極區域及鰭。 第示說明以該方法所形成位於半導體裝置 1結構的腑視圖。根據本發明之示範具體實施 例’於埋職氧化層12〇上鄰近於絲 q 、鰭結構2〗0之端點可形成 源極£域220及汲極區域230。 第2B圖係於第2A圖中沿荽綠A 闻一主-从 考線A-A，之橫截面圖，該 圖不表不鰭結構210之形成。如 .1/1Λ Q 次上所述，可經由蝕刻介電 層140及石夕層130以形成包含且古 、A ，、有介電覆層 140(dielectric cap)之矽鰭i3〇(si】icon ηη)的鳍結構 第3圖係依照本發明之示笳 01Λ ,. 把具體實施例，說明鰭結構 210上方之閘極介電層及閘極树 Τ科之形成的橫截面圖。介 92634 8 1338328 電層可形成於矽鰭130之暴露側表面上。例如，如第3圖， 所不’薄的氧化膜310可經熱成長於轉13〇上。該氧化薄、 膜31〇可長成大約50A至ι〇οΑ之厚度並形成於鰭13〇之 暴露側表面上。 在氧化薄膜3H)形成後，可將閘極材料層沉積於半導 體裝置100之上。參照第4圖，開極材料層可包括非晶石夕 之薄層420以及於其後形成之未摻雜多晶矽層425。層42〇 及425可藉由使用傳統化學氣相沉積法（cvd)或其他習知 技術而沉積。非晶石夕層420可沉積至約為3〇〇A之厚度。擊 更明確地，非晶梦層420可沉積至厚度範圍大約為2〇〇a 至600A。多晶矽層425可沉積至厚度範圍大約為2〇〇a至 1000A。該厚度將可依據鰭或堆疊之高度而改變。 層420及425，尤其是層425，可於之後經平面化。 與本發明之觀點一致的，閘極材料層42〇及425可於平面 化過程中利用非晶矽層420與多晶矽層425之不同研磨速 率而經平面化。更具體地，其係藉由利用非晶矽層42〇與瘳 夕bb石夕層425之間不同的研磨速率而控制非晶矽層可 保留於鰭210上之量。 CMP(Chemical Mechanical p〇lishing ;化學機械研磨） 為一種已知可使用於將半導體表面平面化之平面化技術。 於CMP過程中，將晶圓表面朝下放置於旋轉平台上。該 晶圓以承載體適當地支承，並以相同於平台之方向旋轉。 平台之表面上係一研磨墊，於其上具有研磨液。該研磨液 可包括在載體溶液（carrier solution)中具有氧化妙顆粒 92634 9 1338328 ' (silica particle)之膠體溶液。研磨液之化學組成及酸鹼值 • (PH)會影響CMP程序之效能。於本發明之示範實施例中， 係選擇相較於多晶矽層，其對於非晶矽層具有低研磨速率 之特定研磨液。使用於CMP之研磨液為該項技藝中所眾 所周知且通常為可購得的。許多商業上可購得且與研磨料 例如氧化矽顆粒一起使用於氧化CMP之研磨液，係可經 -化學修飾而以不同速率研磨非晶矽及多晶矽層。研磨液可 y有7至12之間之不同之ph值。非晶矽層之移除速率可由 5〇A/min變化至2000A/min，而非晶矽層之移除速率則可 由 50〇A/min 變化至 6000A/min。 第5圖係說明於最初時期之平面化完成後，閘極材) 層420及425之平面化的橫截面圖。如第5圖所示，多^ 矽層425經最初的平面化後’致使鰭21〇上之多晶矽層^ 的突出部位降低。第6圖圖示說明經進一步CMp程序後 =半導體裝置此時，非晶石夕層傷之較高表面係暴 路表鰭210上方之區域中。因為相較於多晶石夕層化 過程對於非晶料42G具有相對較慢之研磨速率，故非屋 :層可有效做為自動終止層(aut_tic _ 並^ 、·’貝存在做為21G上方之保護層。於⑽期間，小部份 之非晶矽層420亦遭移除係可理解的。於此 極層420及425轩承；& + ® 化柑，非晶矽層420可經使用以指 ::2〗0做為保護终止層_—_〜非, 矽層420延伸至姥91Λ _至，21G上方之最終厚度，如第6圖中之赶 碓/;所不’例如’大約為300A。 92634 10 1^38328 第7圖概略表示半導體裝置1 〇〇之腑視圖，其說明經· 由閘極材料420及425圖案化之閘極結構7〗〇。於CMp過— 程完成後，可將閘極結構71〇圖案化並進行蝕刻。閘極結 構7]0延伸穿過鰭21〇之通道區域。閘極結構71〇可包括 接近於韓210之側邊的閘極部分以及由鑛21 〇所區隔開之 較大的電極部分。閘極結構71〇之電極部分可提供易使用 之電接點（electrical contact)以加偏壓（biasing)或者於其他. 方面控制該閘極部分。 而後再摻雜源極/汲極區域220與230 »例如，將' ^•式或p-型式之雜質（impurities)植入（implanted)源極/汲 極區域22〇與23〇中。基於特定之最後完成裝置（end device) 而求，可選擇特定之植入劑量及能量。熟悉此項技藝者即 可有效完善地進行該以電路需求為基礎之源極/汲極植入 過程，因此為了避免不當混淆本發明之目標要旨，於此將 不揭不該項行為。此外，側壁間隔層（sidewa】lspacers)(未 出不）可於源極/汲極離子植入前隨意地形成以控制該以特鲁丨 定電路需求為基礎之源極/汲極接合的位置。之後再執行活 化退火（activation annealing)以活化源極/汲極區域22〇與 230。 ' 其他實施例 上述之CMP平面化過程可將閘極材料層平面化以形 成半導體裝置100之均勻表面。於某些實施例中，進一步 改善平面化過程’此外，又將虛擬之鰭結構緊鄰放置於鰭 210旁以促進產生更加均勻之層。 11 92634 13^8328 生之FinFET來改善平面化。多間極層可包含一個薄的非 晶矽層，其可於CMP步驟期間做為自動化之平面化级 層。 、、 為了提供本發明之全盤了解，於先前敛述中已說明許 多特定細節’例如敎之材料、結構、化學藥品及步驟等。 然而’本發明並不需要依靠在此所提出之特定細節即可實 施。為了避免不必要地混淆本發明之目標要旨，於其他實 施例中，則未詳細描述習知之製程結構。 八只 根據本發明，使用於製造半導體裝置之介電層及導電 層可藉由傳統之_技術沉積。例如，金屬化技^，可= 用如各種不同型式之化學氣相沉積（CVD)步驟，包括低壓 化學氣相沉積法（LPCVD)以及輔助化學氣相沉積法 (ECVD)。 本發明適用於半導體裝置之製造且尤其適用於具有 100奈米& 1GG奈米以下之設計特徵的半導體裝置，其導 致電晶體及電路速率之增加以及可靠度之改善。本發明適 用於任何各種不同型式之半導體裝置的形成，因此，為了 避免混f本發狀目標要旨，於此並未敘述其細節。於本 發明之實行上’使用了傳統之微影（ph_mh。㈣仏)及姓 d技術因此，在此並未詳細描述該技術之細節。 於此揭示中，僅陳述本發明之較佳具體實施例及苴某 些多用途之範例。須了解本發明可使用於各種不同之其他 組合及環境中，且可於本文所述發明概念之領域範圍内進 92634 14 1338328
I 【圖式簡單說明】’ 附圖中，其中具有相同參考編號之元件於全文中表示 相似元件。 ’' 第1圖表示範例半導體裝置之橫截面圖； 第2A圖表示形成於第】圖所示之半導體裝置上之鰭 結構的腑視圖； s 々第2B圖表示於第2A圖中沿著線α·α，之橫截面圖； 第3圖表不形成於第2Β圖所示之鰭上的閉極介電層 之橫截面圖； | 第4圖表示沉積於第3圖所示之鰭上方的問極材料層 (gate material layers)之橫截面圖； « 5圖表示第4圖之閑極材料層於最初平面 截面圖； 第6圖表示第5圖之閘極材料層於進一步平面化 橫截面圖； 一第7圖概略表示FinFET之腑視圖，其顯現由第石圖 所示之閉極材料為樣本所綠得之閘極結構； 第8圖表示虛擬鰭（dummy fjns)之橫截面圖； 第9圖係於概念上表示半導體裝置上之線陣列“η ' array of Hnes)，包括虛擬結構之圖； 第1〇圖係於概念上表示半導體裝置上另一個虛擬結 構之圖；以及 第II至14圖表示通孔（vias)形成之橫截面圖。 【主要元件符號說明】 92634 15

Claims (1)

  1. 、申請專利範圍： — 〜種半導體裝置之製造方法，包括 於絕緣體上形成鰭結構（210);丨 第93116645號專利申請案 (96年6月5曰） ,於至少部份之該鰭結構以及部份之該絕緣體的上 ^成閘極、..D構’該閘極結構包含第一層（42〇)及形成於 ^第—層上方之第二層（425);以及 藉由執行该閘極結構之化學機械研磨（CMp)而將該 間極結構平面化，該閘極結構之該卜層（42G)之平面化 ，率係比該閑極結構之該第二層（425)之平面化速率 =，該平面化過程會持續直至該第一層之上表面暴露於 該鰭上方之區域中。 ^申請專利範㈣1項之方法，其中，該祕結構之形 成步驟包括： 儿積包含非晶矽之該第一層（42〇);以及 /儿積包含未摻雜之多晶矽之該第二層（425)。 如申請專利範圍第2項之方法，其+，該第—層係經沉 積至厚度祀圍大約為2GG至8GGA且該第二層係經沉積 至厚度範圍大約為200至100〇A。 如申請專利範圍第1項之方法，其中，該化學機械研磨 (CMP)包括使用研磨液將該開極結構平面化，該方法 一步包括： 選擇該研磨液使該第—層之平面化速率約為 2000A/minute且該第二層之平面化速率約為 5〇A/minute。 92634修正本 17 338328 第93116645號專利申請案 5. 如申請專利範圍第1項之方法，其 脒年M5日; 鰭狀場效電晶體（FinFET)。 、中，該半導體裝置係 6. 如申請專利範圍第丨項之方法，其 使用包含矽膠體研磨料且對从，該平面化步驟係 範圍介於7至12之間之研;^物^高選擇性以及PH 7. 一種半導體裝置，包括形成於絕緣體^ 構（210)，該鰭結構（21〇)包括第一及 山之鰭結 之該鰭結構係做為該半導體裳而至）部份 :置包括·· 直十之通道，該半導體裝 ⑷⑴形成於至少部份之該㈣構上方的非晶Μ 形成於部份之該非晶石夕層（42〇)周圍之多晶石夕層 (425)，該非w層（)突出通過軸結構 二 之該多晶矽層，· 連結至該籍結構之第一端的源極區域⑽）；以及 連結至該鰭結構之第二端的汲極區域。 8. 如申請專利範圍第7項之半導體裝置，其中，該半導體 裝置係鰭狀場效電晶體（FinFET)。 9. 如申請專利範圍帛7項之半導體裝置，其中，位於該鳍 結構（2 10)上方區域中之該非晶矽層（42〇)的厚度約為 300A。 10_如申請專利範圍第7項之半導體裝置，其中，該非晶矽 層（420)以及該多晶矽層（425)構成該半導體裝置之 材料層。 18 92634修正本
TW093116645A 2003-06-12 2004-06-10 Dual silicon layer for chemical mechanical polishing planarization TWI338328B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/459,579 US6756643B1 (en) 2003-06-12 2003-06-12 Dual silicon layer for chemical mechanical polishing planarization

Publications (2)

Publication Number Publication Date
TW200503095A TW200503095A (en) 2005-01-16
TWI338328B true TWI338328B (en) 2011-03-01

Family

ID=32508107

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093116645A TWI338328B (en) 2003-06-12 2004-06-10 Dual silicon layer for chemical mechanical polishing planarization

Country Status (8)

Country Link
US (3) US6756643B1 (zh)
JP (1) JP2007500952A (zh)
KR (1) KR101123377B1 (zh)
CN (1) CN100477258C (zh)
DE (1) DE112004001030B4 (zh)
GB (1) GB2418534B (zh)
TW (1) TWI338328B (zh)
WO (1) WO2004112146A1 (zh)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091068B1 (en) * 2002-12-06 2006-08-15 Advanced Micro Devices, Inc. Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization
US7087506B2 (en) * 2003-06-26 2006-08-08 International Business Machines Corporation Method of forming freestanding semiconductor layer
US7224029B2 (en) * 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
WO2005091374A1 (ja) * 2004-03-19 2005-09-29 Nec Corporation 半導体装置及びその製造方法
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7388257B2 (en) * 2004-09-01 2008-06-17 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
KR100678476B1 (ko) 2005-04-21 2007-02-02 삼성전자주식회사 씬 바디의 활성 영역 상에 적어도 두 개의 게이트 실리콘 패턴들을 갖는 더블 게이트 트랜지스터들 및 그 형성방법들
KR100657824B1 (ko) 2005-12-27 2006-12-14 주식회사 하이닉스반도체 핀 트랜지스터 및 그 제조 방법
US7919364B2 (en) * 2006-07-11 2011-04-05 Nxp B.V. Semiconductor devices and methods of manufacture thereof
US8203182B2 (en) * 2007-03-14 2012-06-19 Nxp B.V. FinFET with two independent gates and method for fabricating the same
JP5371144B2 (ja) * 2007-06-29 2013-12-18 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の作製方法、並びに電子機器
US20090050975A1 (en) * 2007-08-21 2009-02-26 Andres Bryant Active Silicon Interconnect in Merged Finfet Process
US8497210B2 (en) 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
CN102479701B (zh) * 2010-11-30 2015-06-24 中国科学院微电子研究所 化学机械平坦化方法和后金属栅的制作方法
US8252689B2 (en) 2010-11-30 2012-08-28 Institute of Microelectronics, Chinese Academy of Sciences Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process
US20130189841A1 (en) * 2012-01-20 2013-07-25 Applied Materials, Inc. Engineering dielectric films for cmp stop
US9647066B2 (en) 2012-04-24 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy FinFET structure and method of making same
CN103426757B (zh) * 2012-05-15 2016-01-06 中芯国际集成电路制造(上海)有限公司 Ω形鳍式场效应晶体管的形成方法
CN103489780B (zh) * 2012-06-13 2016-02-17 中芯国际集成电路制造(上海)有限公司 鳍式场效应管基体的形成方法及鳍式场效应管
CN104008967B (zh) * 2013-02-25 2017-06-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9087796B2 (en) 2013-02-26 2015-07-21 International Business Machines Corporation Semiconductor fabrication method using stop layer
KR20150021811A (ko) * 2013-08-21 2015-03-03 삼성전자주식회사 반도체 소자의 제조방법
US20150200111A1 (en) * 2014-01-13 2015-07-16 Globalfoundries Inc. Planarization scheme for finfet gate height uniformity control
US9472572B2 (en) * 2014-05-06 2016-10-18 Globalfoundries Inc. Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins
CN105161418B (zh) * 2014-06-12 2019-04-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US9773871B2 (en) * 2015-11-16 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
KR102647695B1 (ko) * 2016-08-12 2024-03-14 삼성디스플레이 주식회사 트랜지스터 표시판 및 그 제조 방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260647A (ja) * 1993-03-04 1994-09-16 Sony Corp Ｘｍｏｓトランジスタの作製方法
JP2823819B2 (ja) * 1994-06-27 1998-11-11 松下電器産業株式会社 半導体装置およびその製造方法
JP3607431B2 (ja) * 1996-09-18 2005-01-05 株式会社東芝 半導体装置およびその製造方法
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
JP4389359B2 (ja) * 2000-06-23 2009-12-24 日本電気株式会社 薄膜トランジスタ及びその製造方法
US6630388B2 (en) * 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6787439B2 (en) * 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization

Also Published As

Publication number Publication date
TW200503095A (en) 2005-01-16
WO2004112146A1 (en) 2004-12-23
US20050056845A1 (en) 2005-03-17
KR20060013570A (ko) 2006-02-10
GB2418534A (en) 2006-03-29
JP2007500952A (ja) 2007-01-18
GB0524314D0 (en) 2006-01-04
GB2418534B (en) 2007-01-31
US6982464B2 (en) 2006-01-03
US6756643B1 (en) 2004-06-29
CN1806340A (zh) 2006-07-19
CN100477258C (zh) 2009-04-08
US6812076B1 (en) 2004-11-02
DE112004001030B4 (de) 2008-09-25
DE112004001030T5 (de) 2006-06-01
KR101123377B1 (ko) 2012-03-27

Similar Documents

Publication Publication Date Title
TWI338328B (en) Dual silicon layer for chemical mechanical polishing planarization
TWI287867B (en) Independently accessed double-gate and tri-gate transistors in same process flow
KR101062986B1 (ko) Ｆｉｎｆｅｔ내의 게이트 영역의 다단계 화학 기계 연마
TWI311371B (en) Double gate semiconductor device having separate gates
US7972914B2 (en) Semiconductor device with FinFET and method of fabricating the same
US7449733B2 (en) Semiconductor device and method of fabricating the same
KR101079348B1 (ko) ＦｉｎＦＥＴ 디바이스에 게이트를 형성하고 ＦｉｎＦＥＴ디바이스의 채널 영역의 핀을 가늘게 하는 방법
TWI267924B (en) Improved MOS transistor
TW564468B (en) Dual gate logic device
KR100526887B1 (ko) 전계효과 트랜지스터 및 그의 제조방법
US8642403B1 (en) Replacement contacts for all-around contacts
US7781274B2 (en) Multi-gate field effect transistor and method for manufacturing the same
US20050272190A1 (en) Methods of fabricating fin field-effect transistors having silicide gate electrodes and related devices
KR100653536B1 (ko) 반도체 소자의 핀 전계효과 트랜지스터 제조방법
KR20020037297A (ko) 전계 효과 트랜지스터 및 그 형성 방법
TWI251342B (en) Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same
US8378395B2 (en) Methods of fabricating field effect transistors having protruded active regions
US7704838B2 (en) Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate MOSFET
JP3358544B2 (ja) 電界効果型トランジスタの製造方法
US8530972B2 (en) Double gate MOSFET with coplanar surfaces for contacting source, drain, and bottom gate
TWI518792B (zh) 半導體製程
WO2014036676A1 (zh) 多次可编程半导体器件及其制造方法
US6921940B2 (en) MOS transistor and fabrication method thereof
TWI377672B (en) Vertical soi device with pseudo tri-gate and the method for making the same
CN109698163A (zh) 一种半导体器件及其制造方法

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent