DE102005051206B4 - Speichersystem, Halbleiterspeicherbauelement und Abtastsignalerzeugungsverfahren - Google Patents

Speichersystem, Halbleiterspeicherbauelement und Abtastsignalerzeugungsverfahren Download PDF

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Publication number
DE102005051206B4
DE102005051206B4 DE102005051206A DE102005051206A DE102005051206B4 DE 102005051206 B4 DE102005051206 B4 DE 102005051206B4 DE 102005051206 A DE102005051206 A DE 102005051206A DE 102005051206 A DE102005051206 A DE 102005051206A DE 102005051206 B4 DE102005051206 B4 DE 102005051206B4
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DE
Germany
Prior art keywords
signal
semiconductor memory
command
read
preamble
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102005051206A
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German (de)
English (en)
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DE102005051206A1 (de
Inventor
Kwang-Il Yongin Park
Seong-Jin Seongnam Jang
Ho-young Yongin Song
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102005051206A1 publication Critical patent/DE102005051206A1/de
Application granted granted Critical
Publication of DE102005051206B4 publication Critical patent/DE102005051206B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

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  • Dram (AREA)
DE102005051206A 2004-10-19 2005-10-18 Speichersystem, Halbleiterspeicherbauelement und Abtastsignalerzeugungsverfahren Expired - Fee Related DE102005051206B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2004-0083745 2004-10-19
KR1020040083745A KR100568546B1 (ko) 2004-10-19 2004-10-19 메모리 시스템, 반도체 메모리 장치, 및 이 시스템과장치의 출력 데이터 스트로우브 신호 발생 방법

Publications (2)

Publication Number Publication Date
DE102005051206A1 DE102005051206A1 (de) 2006-04-27
DE102005051206B4 true DE102005051206B4 (de) 2009-08-27

Family

ID=36129183

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102005051206A Expired - Fee Related DE102005051206B4 (de) 2004-10-19 2005-10-18 Speichersystem, Halbleiterspeicherbauelement und Abtastsignalerzeugungsverfahren

Country Status (6)

Country Link
US (3) US7362648B2 (https=)
JP (1) JP4860231B2 (https=)
KR (1) KR100568546B1 (https=)
CN (1) CN100405327C (https=)
DE (1) DE102005051206B4 (https=)
TW (1) TWI291701B (https=)

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US7280417B2 (en) * 2005-04-26 2007-10-09 Micron Technology, Inc. System and method for capturing data signals using a data strobe signal
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US8054928B2 (en) * 2005-11-14 2011-11-08 Ati Technologies, Inc. Programmable preamble system and method
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WO2008079910A2 (en) * 2006-12-20 2008-07-03 Rambus Inc. Strobe acquisition and tracking
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KR100883140B1 (ko) * 2007-11-02 2009-02-10 주식회사 하이닉스반도체 데이터 출력 제어회로, 반도체 메모리 장치 및 그의 동작방법
KR101529291B1 (ko) 2008-02-27 2015-06-17 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 플래시 메모리시스템
KR101040242B1 (ko) 2008-10-13 2011-06-09 주식회사 하이닉스반도체 데이터 스트로브 신호 생성장치 및 이를 이용하는 반도체 메모리 장치
US8250287B1 (en) * 2008-12-31 2012-08-21 Micron Technology, Inc. Enhanced throughput for serial flash memory, including streaming mode operations
US9665507B2 (en) 2010-07-22 2017-05-30 Rambus Inc. Protocol including a command-specified timing reference signal
KR101780422B1 (ko) 2010-11-15 2017-09-22 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
CN103312302B (zh) * 2013-06-24 2016-02-03 浙江禾川科技股份有限公司 单主站多从站结构的通信系统和多路扫描选通信号发生器
CN109343794B (zh) * 2018-09-12 2021-11-09 杭州晨晓科技股份有限公司 一种存储器的配置方法及配置装置
KR102787562B1 (ko) * 2019-11-21 2025-03-31 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
US11645155B2 (en) * 2021-02-22 2023-05-09 Nxp B.V. Safe-stating a system interconnect within a data processing system
US11816352B2 (en) * 2021-10-22 2023-11-14 Realtek Semiconductor Corporation Electronic device, data strobe gate signal generator circuit and data strobe gate signal generating method
US12223205B2 (en) * 2023-04-13 2025-02-11 Innogrit Technologies Co., Ltd. Systems, methods and devices for reading a memory of a storage device
US12499927B2 (en) 2023-12-26 2025-12-16 Nanya Technology Corporation Memory device with receiver circuit to suppress noise on data strobe signals

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Also Published As

Publication number Publication date
JP2006120307A (ja) 2006-05-11
DE102005051206A1 (de) 2006-04-27
US8004911B2 (en) 2011-08-23
US7733715B2 (en) 2010-06-08
KR100568546B1 (ko) 2006-04-07
TW200625334A (en) 2006-07-16
CN100405327C (zh) 2008-07-23
CN1783028A (zh) 2006-06-07
US20100284231A1 (en) 2010-11-11
TWI291701B (en) 2007-12-21
US7362648B2 (en) 2008-04-22
JP4860231B2 (ja) 2012-01-25
US20080144406A1 (en) 2008-06-19
US20060083081A1 (en) 2006-04-20

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8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20140501