CN87105952A - 导电图的制造方法及其操作 - Google Patents

导电图的制造方法及其操作 Download PDF

Info

Publication number
CN87105952A
CN87105952A CN87105952.5A CN87105952A CN87105952A CN 87105952 A CN87105952 A CN 87105952A CN 87105952 A CN87105952 A CN 87105952A CN 87105952 A CN87105952 A CN 87105952A
Authority
CN
China
Prior art keywords
pattern
conducting film
substrate
pad
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN87105952.5A
Other languages
English (en)
Other versions
CN1021875C (zh
Inventor
间濑晃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of CN87105952A publication Critical patent/CN87105952A/zh
Application granted granted Critical
Publication of CN1021875C publication Critical patent/CN1021875C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/032—Materials
    • H05K2201/0326—Inorganic, non-metallic conductor, e.g. indium-tin oxide [ITO]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49137—Different components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Liquid Crystal (AREA)

Abstract

公开了一种在基底上形成电极图案的改进方法。基底涂覆以一第一导电膜且受烘烤。然后在第一导电膜上叠复一第二导电膜，该第二导电膜修补了第一导电膜可能的裂缝，而且该裂缝在图案中会引起开路。

Description

本发明涉及一种导电图的制造方法，更详细地说，涉及一种导电图制造方法的改进，该改进能使得用该方法制造的图案更为可靠。
到现在为止，对于制造包括一对玻璃基底和含有地址线和信号线以产生矩阵排列的电极图案的液晶器件，操作人员所关心的目标是怎样在基底上形成图案而无缺陷，且图案有高度的可靠性。该器件通常还包括用以激励液晶器件的集成（IC）电路片。一直所考虑的问题是IC电路片和图案之间连接的简化和可靠性。特别是图案是在玻璃基底上形成的情形下，在图案中很可能出现导致电路断开的裂缝。
因此本发明的一个目的是提供一种用以制造可靠的电路图案的方法。
为了达到本发明的目的，图案是用双层薄膜制成的。
图1（A）至图1（D）是说明根据本发明制造导电图的方法的横截面图。
图2（A）和图2（B）是说明根据本发明形成的图案的平面图和局部横截面图。
图3（A）和图3（B）是说明根据本发明的IC电路片和导电图之间的接触部分的局部横截面图。
图4（A）和图4（B）是使用于根据本发明的方法中的温度曲线图。
图5（A）至图5（C）是说明根据本发明的方法的横截面图。
图6是说明在IC电路片和用图5（A）至图5（C）所例举的方法所制造的导电图之间的接触部分的横截面图。
参阅图1（A）至图1（D），图中示出了一种根据本发明在基底上形成导电图的方法，该基底用以将一IC电路片安装于其上。在液晶器件的玻璃 基底上（图中只示出其一部分）用导电糊膏以胶版丝网印刷术（offsetscreen    printing）形成一导电图〔图1（A）〕。形成图案的导电糊膏是通过用油乳胶与联邦德国一家名为德特米朗（Detmeron）的工厂销售的“涂覆用银糊膏”（产品号：61900234）相混合配制而成。图案的厚度为10微米。然后，基底根据图4（A）所示的温度曲线在氮气中烘干，以致形成一接触区2a和一基本上由银组成的烧结区〔图1（B）〕。而且，以同样的方式通过印刷和烘干，在图案的一部分上形成另一图案而成为一厚的部分〔图1（C）和图1（D）〕。在烘干以后厚的部分的厚度为30微米。代替印刷法，图案可以用喷涂ITO的方法形成而具有良好接触性和导电性，图2（A）和图2（B）是表示按上述方法在基底上形成的整个图案的平面图和横截面图。
在形成图案以后，将混合有平均直径为15微米的镍粒的环氧树脂透明胶合剂涂在基底的表面上，该基底表面是面向IC的底面和电极垫。每5克胶合剂加进50毫克的镍粒。然后，IC电路片以其铝垫与图案的厚的部分的相应的垫相接触而安装在基底上，而环氧树脂在180℃的温度下硬化，同时用一夹具以3千克的力将IC压紧于基底20分钟。在安装IC电路片的过程中，IC电路片与基底上图案的对准是通过透明树脂从基底底部观察两者来校验的。
能用紫外光来固化的树脂也可以用作胶合剂。在这方案中，树脂是透过透明基底用紫外光来照射。
图3（A）是表示在环氧胶合剂硬化后IC电路片5与基底1的接触的局部横截面图。在铝垫8和厚的部分3的顶部之间的间距预定为3微米，镍粒汇集在该间隙中而使接触电阻较低。包含在环氧树脂内的其他微粒位于IC电路片和基底之间的具有30微米间距的间隔内，而不会损害IC电路片和基底1上的图案2。厚的部分的面积最好是小于图案的相应的垫的面积。
然后，说明本发明的第二实施例。在以如上述实施例的图案2的同样方式用印刷和烘干的方法形成图案以后，用德特米朗厂出售的一种导电胶合剂DAP1（61901143号）涂敷在规定的部分来形成厚的部分3。然后，IC电路片以其铝垫接触图案的厚的部分的相应接合区域而安装在基底上，且用一夹具将IC电路片压在基底上，而基底根据图4（B）所示的温度曲线被烘干。图3（B）是表示根据本实施例的IC电路片和图案之间电气连接的横截面图。通过此实施例，本发明的方法带来了这样的优点：安装IC电路片且使得与IC电路片有必需的接触的加工步骤只需几个。
参阅图5（A）至图5（C），叙述本发明的第三个实施例。在图5（A）中，玻璃基底1是通过印刷方法用散布在酚树脂中的铜粒构成的导电糊膏来涂覆，以便形成一规定的图案11，图案11包括用以与IC电路片的对应垫相接触的电极线。铜粒的平均直径为5-10微米。这导电糊膏涂层然后在60℃的温度下被烘烤10分钟，且通过收缩变薄。该烘干层11可能有裂缝12。
然后，另一层铜导电糊膏13是通过在烘干的铜层上用印刷方法而被叠加在层11上，如图5（B）所示。叠加的铜层也在60℃的温度下被烘烤10分钟。裂缝12必须通过这一叠加的图案得到修补。双层图案散布的厚度约为30微米。双层图案然后受压以制成平的上表面14。在压制以后双层图案的厚度约成为20微米。在图案上安装一IC电路片，电路片与图案相接触的电极垫用镀的方法产生金的凸缘，IC电路片被压在基底上用胶合树脂将其固定就位。
尽管已对几个实施例作出了说明，但本发明仅受所附权利要求书的限定，而不应受特殊的实例的限制。

Claims (10)

1、一种在基底上制造电极图案的方法，其特征在于，该方法包括：
用第一导电膜以电路的电极图案形式涂覆所述基底；以及
用第二导电膜叠复在所述第一导电膜上来涂覆所述基底，所述第二导电膜是设计成起所述电路的完整图案的作用，即使这对所述第一导电膜来说不是这样的。
2、根据权利要求1所述的方法，其特征在于，在所述第一和第二导电膜的所述涂覆步骤后，分别都有烘烤步骤。
3、根据权利要求2所述的方法，其特征在于，烘烤温度是随着时间而改变的。
4、根据权利要求2所述的方法，其特征在于，该方法还包括一压制步骤，以使包括所述第一和第二导电膜的双层图案的上表面平坦。
5、一种制造在基底上包括IC电路片的电路的方法，该方法包括：
在所述基底上形成一导电图;
将胶合剂涂在所述基底表面的准备在上面安装所述IC电路片的部分上;以及
将所述IC电路片安装在所述表面部分上，以其电极垫与所述图案的相应的电极垫相接触，
所述方法的特征在于，所述胶合剂混合有金属微粒。
6、根据权利要求5所述的方法，其特征在于，所述金属微粒是银粒。
7、根据权利要求6所述的方法，其特征在于，所述图案的所述相应垫是增厚的。
8、根据权利要求7所述的方法，其特征在于，一导电层是形成在所述图案的要与所述IC电路片的垫相接触的部分上，以便构成所述增厚的垫。
9、根据权利要求7所述的方法，其特征在于，所述IC电路片的各垫的面积是小于所述图案的相应的垫的面积。
10、一种在液晶器件的玻璃基底上制造电极图案的方法，其特征在于，该方法包括：
用第一导电膜以电路的电极图案形式涂覆所述基底;
烘烤所述第一导电膜;
用第二导电膜叠复在所述第一导电膜上来涂覆所述基底，所述第二导电膜是设计成起所述电路的完整图案的作用，即使这对所述第一导电膜来说不是这样的，
烘烤所述第一和第二导电膜;
压第二导电膜的上表面，以使所述上表面平坦;以及
安装一用以激励所述液晶器件的IC电路片，以其垫与所述图案的相应的垫相接触，IC垫的底表面涂有金凸缘。
CN87105952.5A 1986-12-24 1987-12-23 导电图形的制造方法 Expired - Lifetime CN1021875C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61310493A JPS63160352A (ja) 1986-12-24 1986-12-24 半導体装置の実装方法
JP310493/86 1986-12-24

Publications (2)

Publication Number Publication Date
CN87105952A true CN87105952A (zh) 1988-07-27
CN1021875C CN1021875C (zh) 1993-08-18

Family

ID=18005889

Family Applications (1)

Application Number Title Priority Date Filing Date
CN87105952.5A Expired - Lifetime CN1021875C (zh) 1986-12-24 1987-12-23 导电图形的制造方法

Country Status (4)

Country Link
US (3) US6383327B1 (zh)
EP (1) EP0272678A3 (zh)
JP (1) JPS63160352A (zh)
CN (1) CN1021875C (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1324933C (zh) * 2003-01-14 2007-07-04 夏普株式会社 布线材料、布线基板及其制造方法以及显示面板
CN102332406A (zh) * 2011-08-30 2012-01-25 华东光电集成器件研究所 集成电路导电胶图形制作方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4627843B2 (ja) 1999-07-22 2011-02-09 株式会社半導体エネルギー研究所 半導体装置
JP2001053283A (ja) * 1999-08-12 2001-02-23 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
US7361027B2 (en) * 2002-12-25 2008-04-22 Semiconductor Energy Laboratory Co., Ltd. Contact structure, display device and electronic device
DE102004019412A1 (de) * 2004-04-19 2005-11-03 Man Roland Druckmaschinen Ag Verfahren zum Drucken elektrischer und/oder elektronischer Strukturen und Folie zur Verwendung in einem solchen Verfahren
US7276453B2 (en) * 2004-08-10 2007-10-02 E.I. Du Pont De Nemours And Company Methods for forming an undercut region and electronic devices incorporating the same
US7916263B2 (en) 2004-12-02 2011-03-29 Semiconductor Energy Laboratory Co., Ltd. Display device
US7166860B2 (en) * 2004-12-30 2007-01-23 E. I. Du Pont De Nemours And Company Electronic device and process for forming same
KR101003585B1 (ko) * 2008-06-25 2010-12-22 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
JPWO2014080470A1 (ja) * 2012-11-21 2017-01-05 住友理工株式会社 柔軟導電部材およびそれを用いたトランスデューサ
KR101513642B1 (ko) * 2013-08-21 2015-04-20 엘지전자 주식회사 반도체 디바이스
KR101509425B1 (ko) 2013-08-29 2015-04-08 (주)에프씨아이 컨덕티브 필름을 포함하는 반도체 구조
KR20160051834A (ko) 2013-09-06 2016-05-11 솔베이 스페셜티 폴리머스 이태리 에스.피.에이. 전기 전도성 조립체

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3079282A (en) * 1960-05-24 1963-02-26 Martin N Halier Printed circuit on a ceramic base and method of making same
JPS557022B1 (zh) * 1968-05-10 1980-02-21
US3892635A (en) * 1971-10-28 1975-07-01 Enthone Pre-conditioner and process
NL163370C (nl) 1972-04-28 1980-08-15 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting met een geleiderpatroon.
US3983284A (en) * 1972-06-02 1976-09-28 Thomson-Csf Flat connection for a semiconductor multilayer structure
US4113578A (en) * 1973-05-31 1978-09-12 Honeywell Inc. Microcircuit device metallization
US4113981A (en) * 1974-08-14 1978-09-12 Kabushiki Kaisha Seikosha Electrically conductive adhesive connecting arrays of conductors
JPS5182329A (en) * 1975-01-17 1976-07-19 Nippon Paint Co Ltd Ototsumoyono totsuchobuno osaenarashihoho
JPS51102466A (ja) * 1975-03-06 1976-09-09 Suwa Seikosha Kk Handotaisoshinojitsusohoho
JPS5237744A (en) 1975-09-19 1977-03-23 Seiko Epson Corp Electronic desk computer with liquid crystal display
US4201801A (en) * 1976-05-12 1980-05-06 Nippon Paint Co., Ltd. Method of forming a decorative relief pattern
JPS5392465A (en) * 1977-01-24 1978-08-14 Nippon Electric Co Electronic circuit element board
US4427715A (en) * 1978-07-03 1984-01-24 National Semiconductor Corporation Method of forming expanded pad structure
US4327124A (en) * 1978-07-28 1982-04-27 Desmarais Jr Raymond C Method for manufacturing printed circuits comprising printing conductive ink on dielectric surface
US4297004A (en) * 1978-09-20 1981-10-27 Technical Research of Citizen Watch Co., Ltd. Liquid crystal display cell
JPS5670529A (en) * 1979-11-14 1981-06-12 Hitachi Ltd Liquid crystal display unit
EP0054403B1 (en) * 1980-12-12 1985-09-18 Prutec Limited Method of manufacturing photo-voltaic devices
JPS589124A (ja) * 1981-07-09 1983-01-19 Seiko Epson Corp 液晶パネルの電極構造
US4510179A (en) * 1981-08-18 1985-04-09 Matsushita Electric Industrial Co., Ltd. Electrode on heat-resisting and isolating substrate and the manufacturing process for it
DE3136794C2 (de) 1981-09-16 1983-07-28 Siemens AG, 1000 Berlin und 8000 München Lötfähiges Schichtensystem, seine Verwendung und Verfahren zu seiner Herstellung
FR2516739A1 (fr) * 1981-11-17 1983-05-20 Rhone Poulenc Spec Chim Procede de fabrication de circuits electroniques de type hybride a couches epaisses, des moyens destines a la mise en oeuvre de ce procede et les circuits obtenus selon ce procede
JPS58148434A (ja) 1982-02-26 1983-09-03 Mitsubishi Electric Corp 電気部品実装基板の製造方法
JPS58148934A (ja) * 1982-03-02 1983-09-05 Kokusai Denshin Denwa Co Ltd <Kdd> 光伝送路の伝送特性測定方式
JPS58148923A (ja) * 1982-03-02 1983-09-05 Seiko Instr & Electronics Ltd 電子調律器
FR2525209B1 (fr) * 1982-04-16 1986-08-22 Thomson Csf Procede de realisation d'une couche composite metallique sur un substrat ceramique, et couche metallique obtenue par ce procede
NO157212C (no) 1982-09-21 1988-02-10 Pilkington Brothers Plc Fremgangsmaate for fremstilling av belegg med lav emisjonsevne.
JPS6092648A (ja) * 1983-10-26 1985-05-24 Matsushita Electric Ind Co Ltd バンプ形成用基板およびこれを用いたバンプ形成方法
JPS60107845A (ja) * 1983-11-17 1985-06-13 Toshiba Corp 半導体用回路基板
JPS60108822A (ja) * 1983-11-18 1985-06-14 Alps Electric Co Ltd 液晶表示素子の端子接続方法
JPS60180151A (ja) * 1984-02-28 1985-09-13 Narumi China Corp バンプ付基板及びその製作法
JPS60179703A (ja) * 1984-02-28 1985-09-13 Seiko Instr & Electronics Ltd 多色表示装置の製造方法
JPS60238817A (ja) * 1984-05-12 1985-11-27 Citizen Watch Co Ltd 液晶表示装置
JPS6149432A (ja) * 1984-08-18 1986-03-11 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS61173471A (ja) 1985-01-28 1986-08-05 シャープ株式会社 熱圧着コネクタ−
JPS61256657A (ja) * 1985-05-08 1986-11-14 Mitsubishi Electric Corp 厚膜形成方法
JPS629642A (ja) * 1985-07-05 1987-01-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4667401A (en) * 1985-11-26 1987-05-26 Clements James R Method of making an electronic device using an uniaxial conductive adhesive
DE68926448T2 (de) * 1988-10-14 1996-12-12 Matsushita Electric Ind Co Ltd Bildsensor und verfahren zu dessen herstellung
JPH10100303A (ja) 1996-06-07 1998-04-21 Nippon Sheet Glass Co Ltd 透明導電膜付き基板およびそれを用いた表示素子

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1324933C (zh) * 2003-01-14 2007-07-04 夏普株式会社 布线材料、布线基板及其制造方法以及显示面板
CN102332406A (zh) * 2011-08-30 2012-01-25 华东光电集成器件研究所 集成电路导电胶图形制作方法
CN102332406B (zh) * 2011-08-30 2015-12-09 华东光电集成器件研究所 集成电路导电胶图形制作方法

Also Published As

Publication number Publication date
US6383327B1 (en) 2002-05-07
EP0272678A2 (en) 1988-06-29
JPH0432541B2 (zh) 1992-05-29
US7288437B2 (en) 2007-10-30
US20050148165A1 (en) 2005-07-07
JPS63160352A (ja) 1988-07-04
EP0272678A3 (en) 1990-04-25
CN1021875C (zh) 1993-08-18
US20020110637A1 (en) 2002-08-15

Similar Documents

Publication Publication Date Title
CN1021875C (zh) 导电图形的制造方法
EP0100175B1 (en) Chip capacitor having a compliant termination
US5783465A (en) Compliant bump technology
US5332869A (en) Printed circuit board, a method of its fabrication and a method of attaching electronic parts thereto
JPH0128502B2 (zh)
CN1083109C (zh) 液晶显示装置及其制造方法
JPH08279371A (ja) 接続部材および該接続部材を用いた電極の接続構造並びに接続方法
CN100586256C (zh) 陶瓷基板、电子器件及陶瓷基板的制造方法
JP4661914B2 (ja) 電極の接続方法
JP2755696B2 (ja) 半導体装置及びその製造方法
JP3661704B2 (ja) 多層セラミック基板
JPH07201636A (ja) 積層電子部品及びその製造方法
JPH09306231A (ja) 導電性微粒子及び基板
JPH05290946A (ja) 電子部品実装方法
KR100251673B1 (ko) 서로 마주보는 전극들을 상호접속하기 위한 접속시트, 및이 접속시트를 사용하는 전극접속구조 및 접속방법
JPH0661419A (ja) 電子部品及びその接続方法
JP3783791B2 (ja) 接続部材および該接続部材を用いた電極の接続構造・接続方法
JP3895020B2 (ja) 導電性バンプの形成方法
JPH0815154B2 (ja) 半導体素子用バンプ
JP3633203B2 (ja) 接続基板、接続基板の製造方法および表示装置の製造方法
JP3032111B2 (ja) 表示装置の実装構造
JP4473661B2 (ja) 接続部材
JPH08250543A (ja) 半導体装置
JPH0640558B2 (ja) 電子部品装置
JPH01201984A (ja) 配線基板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
C15 Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993)
C17 Cessation of patent right