CN204614786U - 高密度电路薄膜 - Google Patents

高密度电路薄膜 Download PDF

Info

Publication number
CN204614786U
CN204614786U CN201520289542.5U CN201520289542U CN204614786U CN 204614786 U CN204614786 U CN 204614786U CN 201520289542 U CN201520289542 U CN 201520289542U CN 204614786 U CN204614786 U CN 204614786U
Authority
CN
China
Prior art keywords
circuit
upper strata
density
metal pad
metal gasket
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201520289542.5U
Other languages
English (en)
Inventor
胡迪群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of CN204614786U publication Critical patent/CN204614786U/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本实用新型公开了一种高密度电路薄膜，包含下层电路重新布线层和上层电路重新布线层，下层电路重新布线层具有下层电路与下层绝缘层，下层电路具有复数个第一下层金属垫和复数个第一上层金属垫，第一下层金属垫的密度高于第一上层金属垫的密度；上层电路重新布线层设置于下层电路重新布线层的上方，具有上层电路与上层绝缘层，上层电路具有复数个第二下层金属垫与第二上层金属垫，第二下层金属垫电性耦合于第一上层金属垫，第二下层金属垫的密度高于第二上层金属垫的密度。本实用新型适用于晶片封装用。

Description

高密度电路薄膜
技术领域
本实用新型涉及一种高密度电路薄膜，特别是有关于一种晶片封装用高密度电路薄膜；结构内不含硅插入层(silicon interposer)也不含玻璃插入层(glass interposer)。
背景技术
如图1所示，美国专利US2014/0102777A1公开了一种包含有硅插入层(silicon interposer)20的封装基材(package substrate)。硅插入层20具有四个垂直边206，封装材料22包裹着硅插入层20且围绕着四个垂直边206。复数个纵向导通金属200设置于硅插入层20中。绝缘内衬201设置于纵向导通金属200与硅插入层20的中间，提供电性绝缘。上层电路重新布线层21设置于硅插入层20的上方，复数个金属垫210裸露于上方。金属垫210上方为晶片端(chip side)提供晶片(图中未表示)安置用。电路增层25设置于硅插入层20的下方，具有复数个金属垫220设置于下方。复数个锡铅球4设置于下方，每一个锡铅球4分别设置于一个对应的金属垫220的下方。
晶片封装需求愈来愈薄，一个新的技艺必须被开发。本实用新型便是一个新的封装，其中免除了前述晶片封装中硬质玻璃插入层20或是硬质硅插入层20，使得晶片封装变得更薄。
实用新型内容
针对现有技术的上述不足，根据本实用新型的实施例，希望提供一种使得晶片封装变得更薄，能满足晶片封装愈来愈薄之需求的高密度电路薄膜。根据实施例，本实用新型提供的一种高密度电路薄膜，包含下层电路重新布线层和上层电路重新布线层，其中：
下层电路重新布线层具有下层电路与下层绝缘层，下层电路具有复数个第一下层金属垫和复数个第一上层金属垫，第一下层金属垫的密度高于第一上层金属垫的密度；
上层电路重新布线层设置于下层电路重新布线层的上方，具有上层电路与上层绝缘层，上层电路具有复数个第二下层金属垫与第二上层金属垫，第二下层金属垫电性耦合于第一上层金属垫，第二下层金属垫的密度高于第二上层金属垫的密度。
根据一个实施例，本实用新型前述高密度电路薄膜中，进一步包含至少一颗晶片，该晶片电性耦合至第一下层金属垫。
根据一个实施例，本实用新型前述高密度电路薄膜中，进一步包含封装材料，该封装材料封装所述晶片。
根据一个实施例，本实用新型前述高密度电路薄膜中，封装材料具有一个底面与所述晶片的底面为共平面。
根据一个实施例，本实用新型前述高密度电路薄膜中，进一步包含复数个锡铅球，每一个锡铅球分别安置于对应的第二上层金属垫上。
根据一个实施例，本实用新型前述高密度电路薄膜中，进一步包含纤维增强材料，该纤维增强材料填充于下层绝缘层和/或上层绝缘层中。
根据一个实施例，本实用新型前述高密度电路薄膜中，进一步包含第三上层电路重新布线层，第三上层电路重新布线层设置于上层电路重新布线层的上方，具有第三上层电路与第三上层绝缘层，第三上层电路具有复数个第三下层金属垫与复数个第三上层金属垫，第三下层金属垫电性耦合于第二上层金属垫，且第三下层金属垫的密度高于第三上层金属垫的密度。
根据一个实施例，本实用新型前述高密度电路薄膜中，进一步包含一个纳米晶片，该纳米晶片电性耦合于第一下层金属垫。
根据一个实施例，本实用新型前述高密度电路薄膜中，下层电路依据电路设计准则0.1-0.2um制成；上层电路依据电路设计准则1-2um制成；第三上层电路依据电路设计准则10-20um制成。
根据一个实施例，本实用新型前述高密度电路薄膜中，第一下层金属垫的密度是第一上层金属垫的8-12倍；第二下层金属垫的密度是第二上层金属垫的8-12倍；第三下层金属垫的密度是第三上层金属垫的8-12倍。
根据一个实施例，本实用新型前述高密度电路薄膜中，进一步包含纤维增强材料，该纤维增强材料填充于下层绝缘层、上层绝缘层和/或第三上层绝缘层中。
相对于现有技术，如随后的实施例所述，本实用新型技术方案包含下层电路重新布线层RDL1以及上层电路重新布线层RDL2，上层电路重新布线层RDL2制作于下层电路重新布线层RDL1上方。下层电路重新布线层RDL1系依据积体电路设计准则(IC design rules)制成，具有下层电路与下层绝缘层；下层电路具有复数个第一下层金属垫以及复数个第一上层金属垫；其中第一下层金属垫的密度高于第一上层金属垫。上层电路重新布线层RDL2，系依据印刷电路板设计准则(PCB design rules)所制成，具有上层电路与上层绝缘层，上层电路具有复数个第二下层金属垫与复数个第二上层金属垫；其中第二下层金属垫电性耦合于第一上层金属垫，且第二下层金属垫的密度高于第二上层金属垫。本实用新型免除了背景技术中的硬质玻璃插入层20或是硬质硅插入层20，使得晶片封装变得更薄，能满足晶片封装愈来愈薄之需求。
附图说明
图1是常见晶片封装基材的结构示意图。
图2A--2M是根据本实用新型实施例的高密度电路薄膜在制程的不同步骤的结构示意图。
图2N-2S是根据本实用新型实施例的晶片封装在制程的不同步骤的结构 示意图。
图3是根据本实用新型实施例的高密度电路薄膜(一)的结构示意图。
图4是根据本实用新型实施例的高密度电路薄膜(二)的结构示意图。
图5是根据本实用新型实施例的高密度电路薄膜(三)的结构示意图。
其中：4为锡铅球；20为硅插入层；200为纵向导通金属；201为绝缘内衬；206为垂直边；21为上层电路重新布线层；210为金属垫；22为封装材料；220为金属垫；25为电路增层；RDL1、RDL2、RDL3为重新布线层；I为第一暂时承载器；31、311为释放层；32为种子层；33为光阻；341为金属垫；342为电路；343为金属垫；351、451为绝缘层；441为电路；442为金属垫；51为晶片；511为封装材料；52为锡铅球；521为绝缘层(抗焊漆)；53为散热单元；55为纤维增强材料；60为纳米晶片；B01、B02、M01、M02、T01、T02为金属垫。
具体实施方式
下面结合附图和具体实施例，进一步阐述本实用新型。这些实施例应理解为仅用于说明本实用新型而不用于限制本实用新型的保护范围。在阅读了本实用新型记载的内容之后，本领域技术人员可以对本实用新型作各种改动或修改，这些等效变化和修改同样落入本实用新型权利要求所限定的范围。
图2A-2M显示本实用新型的高密度电路薄膜制程一。
图2A显示一个第一暂时承载器I被准备了，第一释放层31涂布于第一暂时承载器I的上方；以及一个种子层32，例如钛/铜(Ti/Cu)，形成于第一释放层31的上方。
图2B显示一个图案化的光阻33形成于种子层32的上方。
图2C显示复数个第一下层金属垫341(第一下层金属垫)形成于种子层32的上方。
图2D显示图案化的光阻33被移除了，然后复数个第一下层金属垫341 呈现出来。
图2E显示金属垫341之间的种子层32被移除。
图2F显示电路342被形成，其系使用下层金属垫341作为起始，依据积体电路设计准则(IC design rules)制成；包含下述步骤：第一绝缘层351涂布于下层金属垫341的上方，然后，依据习知技艺制作电路342与绝缘层。
图2G显示复数个第一上层金属垫343被形成了，其制程包含：第二绝缘层352涂布于电路342的上方，复数个第一上层金属垫343借着习知技艺而制作完成。电路342以及复数个第一上层金属垫343系举例说明，依据设计需求，重新布线电路层可以有更多层，提供电路更复杂的重新布线。第一下层金属垫341、电路342、第一上层金属垫343、与绝缘层，构成第一重新布线电路层RDL1。
图2H显示第一暂时承载器I被移除了，产出第一重新布线电路层RDL1，然后，切割程序被执行，以产出复数个第一重新布线电路层RDL1个别单元。
图2I显示第一重新布线电路层RDL1的个别单元
图2J显示第一暂时承载器II被准备了；第二释放层311涂布于第二暂时承载器II的上方；复数个第一重新布线电路层RDL1，设置于第二释放层311上方。
图2K显示第二下层金属垫441被形成，且系依据印刷电路板设计准则(PCB design rules)制成，且系以第一上层金属垫343作为起始，其制程包含：第三绝缘层451涂布于第一电路重新布线层RDL1的上方与周围，然后，依据习知技艺，制作第二下层金属垫441于第一电路重新布线层RDL1的上方。
本实用新型在PCB制程所使用的绝缘层，可以是Ajinomoto build-up films(ABF)或是Pre-preg(PP)。
图2L显示复数个第二上层金属垫442被形成，其制程包含：第四绝缘层452涂布于第二下层金属垫441的上方；然后，依据习知技艺制成绝缘层452 以及复数个第二上层金属垫442。复数个第二下层金属垫441与复数个第二上层金属垫442，系举例说明；依据不同的设计需求，重新布线电路可以有更多层提供更复杂的电路布线。第二下层金属垫441、第二上层金属垫442、与绝缘层，整体构成第二重新布线电路层RDL2。高密度电路薄膜(RDL1+RDL2)形成于第二释放层311的上方。
图2M显示第二暂时承载器II被移除了，然后产出高密度电路薄膜(RDL1+RDL2)。
图2N-2S显示本实用新型的晶片封装制程。
图2N显示至少一片晶片51安置于下层金属垫341的下方。
图2O显示封装材料511封装晶片51周边与下方。
图2P显示一个薄化程序，磨薄封装基材511使晶片51的底面裸露，提供晶片51散热用。
图2Q显示一个绝缘层(抗焊漆)521设置于RDL2上方，并裸露第二上层金属垫442，复数个锡铅球52被设置了，每一个锡铅球52设置于对应的第二上层金属垫442上方。
图2R显示一个散热单元53设置于晶片51的底面，提供晶片51进一步的散热用。
图2S显示图2R切割以后，产出的一个晶片封装单元。
下述说明本实用新型的高密度电路薄膜制程一，包含下述步骤：
依据IC设计准则，制作下层电路重新布线层RDL1，下层重新布线层RDL1具有下层电路与下层绝缘层；其中的下层电路，具有复数个第一下层金属垫341形成于底面，以及复数个第一上层金属垫343形成于上表面；其中所述之第一下层金属垫341的密度高于第一上层金属垫343的密度；
依据PCB的设计准则，制作上层电路重新布线层RDL2，上层电路重新布线层RDL2包含有第二下层金属垫441与第二上层金属垫442。第二下层金属 垫441电性耦合于第一上层金属垫343，依据制作完成上层电路重新布线层RDL2；其中第二下层金属垫441的密度，高于第二上层金属垫442的密度。
下述说明本实用新型的高密度电路薄膜制程二，包含下述步骤：
准备第一暂时承载器I；
涂布第一释放层31于所述之第一暂时承载器I的上方；
形成第一种子层32于所述之第一释放层31的上方；
形成复数个第一下层金属垫341于所述之种子层32上面；
去除第一下层金属垫341之间的种子层32；
依据IC设计准则，制作下层电路，其系使用所述之复数个底面金属垫341作为起始制作电路；并且制作复数个第一上层金属垫343于上表面；以习知技艺完成下层电路重新布线层RDL1；
移除第一暂时承载器I以释放所述之下层电路重新布线层RDL1；
切割所述之下层电路重新布线层RDL1，以产生复数个RDL1单元；
准备第二暂时承载器II；
涂布第二释放层311于所述之第二暂时承载器II上方；
安排复数个RDL1单元于所述之第二释放层311上方；
依据PCB设计准则，形成上层电路于所述之RDL1上方，其系使用所述之第一上层金属垫343作为起始；并且制作复数个第二下层金属垫441，制作复数个第二上层金属垫442于上表面；最后，制作完成上层电路重新布线层RDL2；
移除第二暂时承载器II以释放高密度电路薄膜(RDL1+RDL2)。
下述说明使用本实用新型高密度电路薄膜封装积体电路晶片的封装制程，包含下述步骤：
准备所述之高密度电路薄膜(RDL1+RDL2)，其系依据图3或是图4所制作者；
安置至少一颗晶片51，设置于所述之第一下层金属垫341的底面；
以封装胶体511封装所述之晶片51；
磨薄所述之封装胶体511使露出所述之晶片51的底面；
安置散热单元53于所述之晶片51的底面；
切割，使产生复数个单元。
如图3所示，本实用新型实施例的高密度电路薄膜(RDL1+RDL2)，厚度非常薄，大约在50-200um；为了提高整体薄片的坚固程度，便于后续封装方便；本实用新型更将纤维增强材料55设置于高密度电路薄膜中的至少一层绝缘层之中。
如图4所示，本实用新型实施例提供另一高密度电路薄膜具有三层RDL结构，包含底层RDL1、中间层RDL2与上层RDL3。其中，底层RDL1系依据电路设计准则0.1-0.2um制成；适合纳米晶片(nanochip)60的封装。中间层RDL2系依据电路设计准则1-2um制成；上层RDL3系依据电路设计准则10-20um制成。
下层电路重新布线层RDL1，具有下层电路与下层绝缘层；下层电路具有复数个第一下层金属垫B01以及复数个第一上层金属垫B02；其中第一下层金属垫B01的密度高于第一上层金属垫B02。
中间层电路重新布线层RDL2，具有中间层电路与中间层绝缘层，中间层电路具有复数个第二下层金属垫M01与复数个第二上层金属垫M02；其中第二下层金属垫M01电性耦合于第一上层金属垫B02，且第二下层金属垫M01的密度高于第二上层金属垫M02。
上层电路重新布线层RDL3，具有上层电路与上层绝缘层，上层电路具有复数个第三下层金属垫T01与复数个第三上层金属垫T02；其中第三下层金属垫T01电性耦合于第二上层金属垫M02，且第三下层金属垫T01的密度高于第三上层金属垫T02。
如图5所示，本实用新型实施例提供的再一高密度电路薄膜(RDL1+RDL2_RDL3)，厚度非常薄，大约在50-200um；为了提高整体薄片的坚固程度，便于后续封装方便；本实用新型更将纤维增强材料55设置于高密度电路薄膜中的至少一层绝缘层之中。

Claims (11)

1.一种高密度电路薄膜，其特征是，包含下层电路重新布线层和上层电路重新布线层，其中：
下层电路重新布线层具有下层电路与下层绝缘层，下层电路具有复数个第一下层金属垫和复数个第一上层金属垫，第一下层金属垫的密度高于第一上层金属垫的密度；
上层电路重新布线层设置于下层电路重新布线层的上方，具有上层电路与上层绝缘层，上层电路具有复数个第二下层金属垫与第二上层金属垫，第二下层金属垫电性耦合于第一上层金属垫，第二下层金属垫的密度高于第二上层金属垫的密度。
2.如权利要求1所述的高密度电路薄膜，其特征是，进一步包含至少一颗晶片，该晶片电性耦合至第一下层金属垫。
3.如权利要求2所述的高密度电路薄膜，其特征是，进一步包含封装材料，该封装材料封装所述晶片。
4.如权利要求3所述的高密度电路薄膜，其特征是，封装材料具有一个底面与所述晶片的底面为共平面。
5.如权利要求4所述的高密度电路薄膜，其特征是，进一步包含复数个锡铅球，每一个锡铅球分别安置于对应的第二上层金属垫上。
6.如权利要求1所述的高密度电路薄膜，其特征是，进一步包含纤维增强材料，该纤维增强材料填充于下层绝缘层和/或上层绝缘层中。
7.如权利要求1所述的高密度电路薄膜，其特征是，进一步包含第三上层电路重新布线层，第三上层电路重新布线层设置于上层电路重新布线层的上方，具有第三上层电路与第三上层绝缘层，第三上层电路具有复数个第三下层金属垫与复数个第三上层金属垫，第三下层金属垫电性耦合于第二上层金属垫，且第三下层金属垫的密度高于第三上层金属垫的密度。
8.如权利要求7所述的高密度电路薄膜，其特征是，进一步包含一个纳米晶片，该纳米晶片电性耦合于第一下层金属垫。
9.如权利要求7所述的高密度电路薄膜，其特征是，下层电路依据电路设计准则0.1-0.2um制成；上层电路依据电路设计准则1-2um制成；第三上层电路依据电路设计准则10-20um制成。
10.如权利要求7所述的高密度电路薄膜，其特征是，第一下层金属垫的密度是第一上层金属垫的8-12倍；第二下层金属垫的密度是第二上层金属垫的8-12倍；第三下层金属垫的密度是第三上层金属垫的8-12倍。
11.如权利要求7所述的高密度电路薄膜，其特征是，进一步包含纤维增强材料，该纤维增强材料填充于下层绝缘层、上层绝缘层和/或第三上层绝缘层中。
CN201520289542.5U 2014-06-18 2015-05-07 高密度电路薄膜 Expired - Fee Related CN204614786U (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201414308702A 2014-06-18 2014-06-18
US14/308,702 2014-06-18
US14/509,395 2014-10-08
US14/509,395 US9799622B2 (en) 2014-06-18 2014-10-08 High density film for IC package

Publications (1)

Publication Number Publication Date
CN204614786U true CN204614786U (zh) 2015-09-02

Family

ID=53189710

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520289542.5U Expired - Fee Related CN204614786U (zh) 2014-06-18 2015-05-07 高密度电路薄膜

Country Status (6)

Country Link
US (2) US9799622B2 (zh)
EP (1) EP2958142B1 (zh)
JP (1) JP6484116B2 (zh)
KR (1) KR101997487B1 (zh)
CN (1) CN204614786U (zh)
TW (1) TWM515202U (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017050464A (ja) * 2015-09-03 2017-03-09 凸版印刷株式会社 配線基板積層体、その製造方法及び半導体装置の製造方法
CN107170730A (zh) * 2016-03-08 2017-09-15 胡迪群 具有双面细线重新分布层的封装基材
US10032702B2 (en) 2016-12-09 2018-07-24 Dyi-chung Hu Package structure and manufacturing method thereof
JP2019016647A (ja) * 2017-07-04 2019-01-31 日立化成株式会社 ファンアウト・ウエハレベルパッケージの仮固定方法
CN113571494A (zh) * 2020-04-28 2021-10-29 群创光电股份有限公司 电子装置及其制作方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538318B (zh) * 2014-12-24 2017-12-19 通富微电子股份有限公司 一种扇出型圆片级芯片封装方法
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
CN104966709B (zh) 2015-07-29 2017-11-03 恒劲科技股份有限公司 封装基板及其制作方法
US9786586B1 (en) 2016-08-21 2017-10-10 Micron Technology, Inc. Semiconductor package and fabrication method thereof
US10002852B1 (en) * 2016-12-15 2018-06-19 Dyi-chung Hu Package on package configuration
JP6783648B2 (ja) * 2016-12-26 2020-11-11 新光電気工業株式会社 配線基板、半導体装置
US10687419B2 (en) 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10902769B2 (en) 2017-07-12 2021-01-26 Facebook Technologies, Llc Multi-layer fabrication for pixels with calibration compensation
US10733930B2 (en) * 2017-08-23 2020-08-04 Facebook Technologies, Llc Interposer for multi-layer display architecture
CN107564900B (zh) * 2017-08-29 2019-09-03 中国电子科技集团公司第五十八研究所 基于射频信号传输的扇出型封装结构及制造方法
US10304716B1 (en) * 2017-12-20 2019-05-28 Powertech Technology Inc. Package structure and manufacturing method thereof
US11798865B2 (en) * 2019-03-04 2023-10-24 Intel Corporation Nested architectures for enhanced heterogeneous integration
KR102706158B1 (ko) * 2019-08-30 2024-09-11 삼성전자주식회사 반도체 패키지 제조 방법
US12015003B2 (en) 2021-09-29 2024-06-18 International Business Machines Corporation High density interconnection and wiring layers, package structures, and integration methods
US12040291B2 (en) * 2021-12-20 2024-07-16 Nxp Usa, Inc. Radio frequency packages containing multilevel power substrates and associated fabrication methods

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162240A (en) 1989-06-16 1992-11-10 Hitachi, Ltd. Method and apparatus of fabricating electric circuit pattern on thick and thin film hybrid multilayer wiring substrate
JPH11289167A (ja) * 1998-03-31 1999-10-19 Nec Corp 多層配線板
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US7038142B2 (en) * 2002-01-24 2006-05-02 Fujitsu Limited Circuit board and method for fabricating the same, and electronic device
JP2004311912A (ja) * 2002-12-06 2004-11-04 Sony Corp 回路基板モジュール及びその製造方法
US7462784B2 (en) 2006-05-02 2008-12-09 Ibiden Co., Ltd. Heat resistant substrate incorporated circuit wiring board
JP5356876B2 (ja) 2008-03-28 2013-12-04 日本特殊陶業株式会社 多層配線基板及びその製造方法
JP2009290124A (ja) * 2008-05-30 2009-12-10 Fujitsu Ltd プリント配線板
JP5550280B2 (ja) * 2009-07-29 2014-07-16 京セラ株式会社 多層配線基板
WO2012009831A1 (zh) * 2010-07-23 2012-01-26 欣兴电子股份有限公司 线路板及其制造方法
US8749254B2 (en) * 2010-11-15 2014-06-10 Advanced Micro Devices, Inc. Power cycling test arrangement
KR101767108B1 (ko) 2010-12-15 2017-08-11 삼성전자주식회사 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법
JP5837783B2 (ja) * 2011-09-08 2015-12-24 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP5977051B2 (ja) * 2012-03-21 2016-08-24 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
TWI499023B (zh) 2012-10-11 2015-09-01 Ind Tech Res Inst 封裝基板及其製法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017050464A (ja) * 2015-09-03 2017-03-09 凸版印刷株式会社 配線基板積層体、その製造方法及び半導体装置の製造方法
CN107170730A (zh) * 2016-03-08 2017-09-15 胡迪群 具有双面细线重新分布层的封装基材
US10032702B2 (en) 2016-12-09 2018-07-24 Dyi-chung Hu Package structure and manufacturing method thereof
JP2019016647A (ja) * 2017-07-04 2019-01-31 日立化成株式会社 ファンアウト・ウエハレベルパッケージの仮固定方法
CN113571494A (zh) * 2020-04-28 2021-10-29 群创光电股份有限公司 电子装置及其制作方法

Also Published As

Publication number Publication date
KR20160011139A (ko) 2016-01-29
US10304794B2 (en) 2019-05-28
KR101997487B1 (ko) 2019-07-08
US20170365573A1 (en) 2017-12-21
EP2958142B1 (en) 2020-03-11
EP2958142A1 (en) 2015-12-23
JP2016004999A (ja) 2016-01-12
US20150371965A1 (en) 2015-12-24
TWM515202U (zh) 2016-01-01
JP6484116B2 (ja) 2019-03-13
US9799622B2 (en) 2017-10-24

Similar Documents

Publication Publication Date Title
CN204614786U (zh) 高密度电路薄膜
CN103904057B (zh) PoP封装结构及制造工艺
CN103887291B (zh) 三维扇出型PoP封装结构及制造工艺
TWM509421U (zh) 封裝單元堆疊模組
CN105118823A (zh) 一种堆叠型芯片封装结构及封装方法
CN103887279B (zh) 三维扇出型晶圆级封装结构及制造工艺
CN205039151U (zh) 一种堆叠型芯片封装结构
CN105140213A (zh) 一种芯片封装结构及封装方法
CN104538318B (zh) 一种扇出型圆片级芯片封装方法
CN102468189A (zh) 半导体封装以及封装半导体器件的方法
CN103915414A (zh) 倒装芯片晶片级封装及其方法
CN103579204A (zh) 包括电容器的封装结构及其形成方法
CN106653628B (zh) 一种半导体存储器及其制作方法
CN107482015B (zh) 一种三维存储器的制备方法及其结构
CN106571344A (zh) 封装胶体包裹的封装基材
CN203659838U (zh) 一种用于PoP封装的散热结构
CN103904056A (zh) 一种PoP封装结构及制造工艺
CN104157619B (zh) 一种新型PoP堆叠封装结构及其制造方法
CN103295926A (zh) 一种基于tsv芯片的互连封装方法
CN103874346B (zh) 一种电路板的制作方法
CN104241217A (zh) 一种芯片背面裸露的扇出型封装结构及制造方法
CN104766806B (zh) 晶圆三维集成的方法
CN204011396U (zh) 一种新型PoP堆叠封装结构
EP2899752A1 (en) Structure and formation method of chip package structure
CN105939573B (zh) 电路板结构及预留盲孔转换成盲孔的方法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150902

Termination date: 20180507

CF01 Termination of patent right due to non-payment of annual fee