CN107170730A - 具有双面细线重新分布层的封装基材 - Google Patents

具有双面细线重新分布层的封装基材 Download PDF

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CN107170730A
CN107170730A CN201710067488.3A CN201710067488A CN107170730A CN 107170730 A CN107170730 A CN 107170730A CN 201710067488 A CN201710067488 A CN 201710067488A CN 107170730 A CN107170730 A CN 107170730A
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redistribution layer
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胡迪群
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Abstract

本发明公开了一种具有双面细线重新分布层的封装基材，包含中间重新分布层、顶部重新分布层和底部重新分布层。顶部重新分布层的顶表面适于至少一个芯片安装，底部重新分布层的底表面适于至少一个芯片安装。中间重新分布层的每个电路的线宽比顶部重新分布层或底部重新分布层的每个电路的线宽宽。顶部重新分布层的顶表面具有适于至少一个芯片安装的多个顶部金属垫，并且底部重新分布层的底表面具有适于至少一个芯片安装的多个底部金属垫，可以实现高密度的系统级封装(SIP)。旁边相邻的芯片，可以通过较短的电路路径相互沟通，并且顶部与底部相邻的芯片，也可以经过较短的电路路径相互沟通。

Description

具有双面细线重新分布层的封装基材
技术领域
本发明涉及一种封装基材，特别涉及一种用于系统级封装(system in package,SIP)的具有双面细线重新分布层(redistribution layer,RDL)的封装基材。
背景技术
如图1所示，现有技术的封装基材中，第一芯片501和第二芯片502被配置在中介层51的顶侧上；中介层51配置在封装基材52的顶侧上；封装基材52配置在系统板53的顶侧上。第一芯片501和第二芯片502之间的信号传递，需要经过一条较长的路径，如虚线55所示。参考图1，从芯片501到芯片502的信号传递路径，从中介层51、封装基材52、系统板53、回到封装基材52、中介层51，然后到达芯片502；这种现有技术的缺点是路径越长、信号越弱。
长久以来，半导体电路研发人员，一直寻求相邻芯片之间的信号传递路径的缩短的研究，本发明便是解决此一问题的先驱。
发明内容
针对现有技术的上述不足，根据本发明的实施例，希望提供一种可以缩短相邻芯片之间的信号传递路径的具有双面细线重新分布层(redistribution layer,RDL)的封装基材。
根据实施例，本发明提供的一种具有双面细线重新分布层的封装基材，包括第一重新分布层、第二重新分布层和第三重新分布层，其中：
第一重新分布层具有埋设在多个第一介电层中的第一电路；所述第一电路包括配置在所述第一重新分布层的顶侧上的多个第一上层金属垫和配置在所述第一重新分布层的底侧上的多个第一下层金属垫；所述第一下层金属垫的密度高于所述第一上层金属垫的密度；所述第一下层金属垫的底侧适于安装至少一个芯片；
第二重新分布层配置在所述第一重新分布层的顶侧上，具有埋设在多个第二介电层中的第二电路；所述第二电路包括配置在所述第二重新分配层的顶侧上的多个第二上层金属垫和配置在所述第二重新分布层的底侧上的多个第二下层金属垫；所述第二电路通过多个第一纵向导通金属电性耦合到所述第一电路；
第三重新分布层配置在所述第二重新分布层的顶侧上，具有埋设在多个第三介电层中的第三电路；所述第三电路通过多个第二纵向导通金属电性耦合到所述第二电路；所述第三电路包括配置在所述第三重新分布层的顶侧上的多个第三上层金属垫和配置在所述第三重新分布层的底侧上的多个第三下层金属垫；所述第三上层金属垫的密度高于所述第三下层金属垫的密度；所述第三上层金属垫的顶侧适于安装至少一个芯片；
所述第二电路的每个电路的线宽比所述第一电路的每个电路的线宽宽；所述第二电路的每个电路的线宽比所述第三电路的每个电路的线宽宽。
根据一个实施例，本发明前述具有双面细线重新分布层的封装基材中，每个第一上层金属垫通过相应的第一纵向导通金属电性耦合到相应的第二下层金属垫；每个第三下层金属垫通过相应的第二纵向导通金属电性耦合到相应的第二上层金属垫。
根据一个实施例，本发明前述具有双面细线重新分布层的封装基材中，所述第二重新分布层具有延伸超出所述第一重新分布层或是所述第三重新分布层中的一个的侧边的延伸区域；以及暴露在第二重新分布层的延伸区域的顶侧上的至少一个连接金属垫。
根据一个实施例，本发明前述具有双面细线重新分布层的封装基材中，还包括软性电路板，该软性电路板具有至少一个金属垫，适于电性耦合到暴露在第二重新分布层的延伸区域上的至少一个顶部金属垫。
根据一个实施例，本发明前述具有双面细线重新分布层的封装基材中，所述第一介电层的最上层与所述第二介电层的最下层直接接触，所述第二介电层的最上层与所述第三介电层的最下层直接接触。
根据实施例，本发明提供的一种具有双面细线重新分布层的封装基材的制作方法，包括如下步骤：
制备暂时承载板，在所述暂时承载板的顶表面上设置释放层；并且在所述释放层的顶表面上设置基底介电层；
在所述基底介电层的顶表面上形成第一重新分布层；所述第一重新分布层具有第一电路埋设于多层第一介电层中；
在所述第一重新分布层的顶表面上形成第二重新分布层；所述第二重新分布层具有第二电路埋设于多层第二介电层中；
在所述第二重新分布层的顶表面上形成第三重新分布层；所述第三重新分布层具有第三电路埋设于多层第三介电层中；
所述第二电路的每个电路的线宽至少是所述第一电路的每个电路的线宽的两倍；并且所述第二电路的每个电路的线宽度是所述第三电路的每个电路的线宽度的至少两倍；以及
所述第一介电层的最上层与所述第二介电层的最下层直接接触、所述第二介电层的最上层与所述第三介电层的最下层直接接触。
根据一个实施例，本发明前述具有双面细线重新分布层的封装基材的制造方法，还包括如下步骤：
从侧边蚀刻所述第三介电层的一部分，暴露所述第二重新分布层的顶表面，并且暴露所述第二重新分布层的顶表面上的至少一个金属垫。
根据一个实施例，本发明前述具有双面细线重新分布层的封装基材的制造方法，还包括如下步骤：
制备另一软性电路板，该软性电路板包括至少一个金属垫暴露在所述软性电路板一侧，适于电性耦合到暴露在所述第二重新分布层的所述延伸区域上的所述至少一个顶部金属垫。
相对于现有技术，本发明具有中间重新分布层(middle RDL)的封装基材中，中间重新分布层(middle RDL)作为核心重新分布层(core RDL)。中间重新分布层被顶部重新分布层(top RDL)和底部重新分布层(bottom RDL)夹在中间。顶部重新分布层的顶表面具有适于至少一个芯片安装的多个顶部金属垫，并且底部重新分布层的底表面具有适于至少一个芯片安装的多个底部金属垫，可以实现高密度的系统级封装(SIP)。旁边相邻的芯片，可以通过较短的电路路径相互沟通，并且顶部与底部相邻的芯片，也可以经过较短的电路路径相互沟通。另外，准备另一软性电路板，软性电路板上具有电路。软性电路板的电路具有第一端，电性耦合到核心重新分配层(core RDL)电路，并且具有第二端，电性耦合到系统板(system board)或是其他的电子组件。
附图说明
图1是现有技术中一种封装基材的结构示意图。
图2是根据本发明实施例的具有双面细线重新分布层的封装基材的结构示意图。
图3A-3G是根据本发明实施例的具有双面细线重新分布层的封装基材的制程图。
其中：200为封装基材；RDL1为第一重新分配层；10为第一电路；1U为第一上层金属垫；1L为第一下层金属垫；D10为第一介电层；201,202,203,204为芯片；RDL2为第二重新分布层；20为第二电路；2U为第二上层金属垫；2L为第二下层金属垫；D20为第二介电层；RDL3为第三重新分布层；30为第三电路；3U为第三上层金属垫；3L为第三下层金属垫；D30为第三介电层；1V为第一纵向导通金属；2V为第二纵向导通金属；24为连接金属垫；24E为延伸部；40为软性电路板；41为金属垫。
具体实施方式
下面结合附图和具体实施例，进一步阐述本发明。这些实施例应理解为仅用于说明本发明而不用于限制本发明的保护范围。在阅读了本发明记载的内容之后，本领域技术人员可以对本发明作各种改动或修改，这些等效变化和修改同样落入本发明权利要求所限定的范围。
如图2所示，本发明的第一实施例提供的具有中间重新分布层RDL2的封装基材200。中间重新分布层RDL2夹在底部重新分布层RDL1和顶部重新分布层RDL3之间。
底部重新分布层(第一重新分布层)RDL1系根据集成电路设计准则(IC designrule)制造。第一重新分布层RDL1具有埋设在多个第一介电层D10中的第一电路10；第一电路10包括多个第一上层金属垫1U和多个第一下层金属垫1L，第一上层金属垫1U配置于第一重新分布层RDL1的上侧，多个第一下层金属垫1L配置于第一重新分布层RDL1的下侧；第一下层金属垫1L的密度高于第一上层金属垫1U的密度；第一下层金属垫1L的底侧适于安装至少一个芯片；图中第一芯片201和第二芯片202作为范例说明，安装在第一重新分配层RDL1的底表面上。
核心重新分配层(第二重新分配层)RDL2系根据印刷电路板的设计准则(PCBdesign rule)制造的，配置在第一重新分配层RDL1的顶侧上，具有埋设在多个第二介电层D20中的第二电路20；第二电路20包括：配置在第二重新分布层RDL2的顶侧上的多个第二上层金属垫2U和配置在第二重新分布层RDL2的底侧上的多个第二下层金属垫2L；第二电路20电性耦合到第一电路10。
顶部重新分布层(第三重新分布层)RDL3系根据集成电路设计准则(IC designrule)所制造的，配置在第二重新分布层RDL2的顶侧上；具有埋设在多个第三介电层D30中的第三电路30；第三电路30电性耦合到第二电路20；第三电路30包括多个第三上层金属垫3L以及多个第三下层金属垫3L，其中第三上层金属垫3L配置于第三重新分布层RDL3的上侧，第三下层金属垫3L配置于第三重新分布层RDL3的下侧。第三上层金属垫3U的密度高于第三下层金属垫3L的密度；第三上层金属垫3U的顶侧适于安装至少一个芯片；图中以第三芯片203和四个芯片204作为范例说明，安装在第三重新分布层RDL3的顶表面上。
第二电路20的每个电路的线宽至少是第一电路10的每个电路的线宽的两倍；并且第二电路20的每个电路的线宽度是第三电路30的每个电路的线宽至少两倍。
每个第一上层金属垫1U通过相应的第一纵向导通金属1V电性耦合到对应的一个第二下层金属垫2L。每个第三下层金属垫3L通过相应的第二纵向导通金属2V电性耦合到相应的一个第二上层金属垫2U。
第二重新分布层RDL2具有一个延伸区域24E，延伸超过第三重新分布层RDL3的一侧；并且至少一个连接金属垫24暴露在第二重新分布层RDL2的延伸区域24E的顶侧上。
一片软性电路板40，用于将封装基材电性耦合到外部的控制系统或另外的电子系统；软性电路板40具有至少一个金属垫41，适于电性耦合到至少一个顶部金属垫24。
如图3A-3G所示，本发明提供的双面安置芯片的封装基材的制作方法，包括以下步骤：
如图3A所示，制备暂时承载板，在暂时承载板的顶表面上设置释放层R1；并且在释放层R1的顶表面上设置基底介电层D0；
如图3B所示，根据半导体设计规则，在基底介电层D0的顶表面上形成第一重新分布层RDL1；RDL1包括埋设在多个第一介电层D10中的第一电路10；
如图3C所示，根据印刷电路板设计规则在第一重新分布层RDL1的顶表面上形成第二重新分布层RDL2；RDL2包括埋设在多个第二介电层D20中的第二电路20；
如图3D所示，根据半导体设计规则，在第二重新分布层RDL2的顶表面上形成第三重新分布层RDL3；RDL3包括埋设在多个第三介电层D30中的第三电路30；其中第二电路20的每个电路的线宽度是第一电路10的每个电路的线宽度的至少两倍；并且第二电路20的每个电路的线宽度是第三电路30的每个电路的线宽度的至少两倍。
如图3E所示，从旁边侧蚀刻第三介电层D30中的一部分，以暴露第二重新分布层RDL2的顶表面，并暴露第二重新分布层RDL2的顶表面上的至少一个金属垫24，以及蚀刻多个顶部开口32以暴露对应的第三上层金属垫3U。
如图3F所示，去除暂时承载板，去除释放层R1，以及形成多个底部开口12以暴露相应的第一下层金属垫1L。
如图3G所示，制备软性电路板，软性电路板40包括至少一个金属垫41，适于电性耦合到暴露在第二重新分布层RDL2的延伸区域24E上的至少一个顶部金属垫24；将芯片201,202安装在第一重新分配层RDL1的底表面上，以及将芯片203,204安装在第三重新分配层RDL3的顶表面上。

Claims (8)

1.一种具有双面细线重新分布层的封装基材，包括第一重新分布层、第二重新分布层和第三重新分布层，其特征是，
第一重新分布层具有埋设在多个第一介电层中的第一电路；所述第一电路包括配置在所述第一重新分布层的顶侧上的多个第一上层金属垫和配置在所述第一重新分布层的底侧上的多个第一下层金属垫；所述第一下层金属垫的密度高于所述第一上层金属垫的密度；所述第一下层金属垫的底侧适于安装至少一个芯片；
第二重新分布层配置在所述第一重新分布层的顶侧上，具有埋设在多个第二介电层中的第二电路；所述第二电路包括配置在所述第二重新分配层的顶侧上的多个第二上层金属垫和配置在所述第二重新分布层的底侧上的多个第二下层金属垫；所述第二电路通过多个第一纵向导通金属电性耦合到所述第一电路；
第三重新分布层配置在所述第二重新分布层的顶侧上，具有埋设在多个第三介电层中的第三电路；所述第三电路通过多个第二纵向导通金属电性耦合到所述第二电路；所述第三电路包括配置在所述第三重新分布层的顶侧上的多个第三上层金属垫和配置在所述第三重新分布层的底侧上的多个第三下层金属垫；所述第三上层金属垫的密度高于所述第三下层金属垫的密度；所述第三上层金属垫的顶侧适于安装至少一个芯片；
所述第二电路的每个电路的线宽比所述第一电路的每个电路的线宽宽；所述第二电路的每个电路的线宽比所述第三电路的每个电路的线宽宽。
2.如权利要求1所述的具有双面细线重新分布层的封装基材，其特征是，每个第一上层金属垫通过相应的第一纵向导通金属电性耦合到相应的第二下层金属垫；每个第三下层金属垫通过相应的第二纵向导通金属电性耦合到相应的第二上层金属垫。
3.根据权利要求2所述的具有双面细线重新分布层的封装基材，其特征是，所述第二重新分布层具有延伸超出所述第一重新分布层或是所述第三重新分布层中的一个的侧边的延伸区域，并且暴露在第二重新分布层的延伸区域的顶侧上的至少一个连接金属垫。
4.根据权利要求3所述的具有双面细线重新分布层的封装基材，其特征是，还包括软性电路板，该软性电路板具有至少一个金属垫，适于电性耦合到暴露在第二重新分布层的延伸区域上的至少一个顶部金属垫。
5.根据权利要求4所述的具有双面细线重新分布层的封装基材，其特征是，所述第一介电层的最上层与所述第二介电层的最下层直接接触，所述第二介电层的最上层与所述第三介电层的最下层直接接触。
6.一种具有双面细线重新分布层的封装基材的制作方法，其特征是，包括如下步骤：
制备暂时承载板，在所述暂时承载板的顶表面上设置释放层；并且在所述释放层的顶表面上设置基底介电层；
在所述基底介电层的顶表面上形成第一重新分布层；所述第一重新分布层具有第一电路埋设于多层第一介电层中；
在所述第一重新分布层的顶表面上形成第二重新分布层；所述第二重新分布层具有第二电路埋设于多层第二介电层中；
在所述第二重新分布层的顶表面上形成第三重新分布层；所述第三重新分布层具有第三电路埋设于多层第三介电层中；其中：
所述第二电路的每个电路的线宽至少是所述第一电路的每个电路的线宽的两倍；并且所述第二电路的每个电路的线宽度是所述第三电路的每个电路的线宽度的至少两倍；以及
所述第一介电层的最上层与所述第二介电层的最下层直接接触、所述第二介电层的最上层与所述第三介电层的最下层直接接触。
7.根据权利要求6所述的具有双面细线重新分布层的封装基材的制造方法，其特征是，还包括如下步骤：
从侧边蚀刻所述第三介电层的一部分，暴露所述第二重新分布层的顶表面，并且暴露所述第二重新分布层的顶表面上的至少一个金属垫。
8.根据权利要求7所述的具有双面细线重新分布层的封装基材的制造方法，还包括如下步骤：
制备软性电路板，具有至少一个金属垫暴露在所述软性电路板一侧，适于电性耦合到暴露在所述第二重新分布层的所述延伸区域上的所述至少一个顶部金属垫。
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