US20140084413A1 - Package substrate and method of fabricating the same - Google Patents
Package substrate and method of fabricating the same Download PDFInfo
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- US20140084413A1 US20140084413A1 US13/965,842 US201313965842A US2014084413A1 US 20140084413 A1 US20140084413 A1 US 20140084413A1 US 201313965842 A US201313965842 A US 201313965842A US 2014084413 A1 US2014084413 A1 US 2014084413A1
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- Prior art keywords
- substrate
- protective layer
- conductive
- insulating protective
- package substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000011241 protective layer Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005553 drilling Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present disclosure relates to package substrates and methods of fabricating the same, and relates to a package substrate having an embedded interposer and a method of fabricating the same.
- the present disclosure provides a package substrate that integrates an interposer and passive components.
- the package substrate may include: a substrate with wirings, a first surface and a second surface opposing the first surface, the first surface including a plurality of conductive pads; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in the insulating protective layer and electrically connected to the substrate, the interposer including a plurality of penetrating conductive vias and a wiring redistribution layer exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate.
- FIG. 1 is a cross-sectional view of a package substrate according to a first embodiment of the present disclosure
- FIGS. 2A to 2C are cross-sectional views of a package substrate according to a second embodiment of the present disclosure.
- FIG. 3 is a cross-sectional view of a package substrate according to a third embodiment of the present disclosure.
- FIG. 4 is a cross-sectional view of a package substrate according to a fourth embodiment of the present disclosure.
- Conductive vias refers to conductive components formed on a substrate, for example, the interposer herein. As shown in the diagrams, the shape of the conductive vias can be columnar.
- FIG. 1 a cross-sectional view of a package substrate 2 according to a first embodiment of the present disclosure is shown.
- a substrate 20 having wirings 200 , a top surface (can be regarded as a first surface) 20 a and a bottom surface (can be regarded as a second surface) 20 b is provided.
- the substrate 20 is a multilayer interconnect base plate.
- the top surface 20 a has a plurality of conductive pads 21 a.
- An interposer 22 and an insulating protective layer 23 are formed on the top surface 20 a.
- the interposer 22 is embedded into the insulating protective layer 23 and exposed from the surface of the insulating protection layer 23 .
- a plurality of passive components 24 are provided on the interposer 22 .
- the interposer 22 is a silicon interposer and has a plurality of penetrating conductive vias 221 and a wiring redistribution layer (RDL) 222 exposed from the insulating protective layer 23 .
- the bottom ends of the conductive vias 221 are each connected to conductive pads 21 a to electrically connect with the wirings 200 , and the passive components 24 are arranged on the wiring redistribution layer 222 to be electrically connected with the interposer 22 .
- the passive components 24 By disposing the passive components 24 on the wiring redistribution layer 222 , when an active component (not shown) such as a semiconductor chip is provided on the wiring redistribution layer 222 , the active component can be assembled in a way that it is closest to the passive components 24 , thereby reducing the distance between the active component and the passive components 24 .
- an active component such as a semiconductor chip
- Signals are transmitted to the substrate 20 through the wiring redistribution layer 222 and the passive components 24 connected in series, and the conductive vias 221 , so that the electrical connection path between the active component and the passive components 24 is made shortest. As a result, the pins of the active component have stable voltage.
- FIGS. 2A to 2C cross-sectional views of a package substrate 3 according to a second embodiment of the present disclosure are shown.
- the second embodiment differs from the first embodiment in the locations and the electrical connection method of the passive components 24 .
- a plurality of holes 230 are formed in the insulating protective layer 23 at locations corresponding to a portion of the exposed conductive pads 21 a by using a fixed-depth mechanical drilling method or a laser drilling method.
- conductive components 231 such as columns are formed in the holes 230 by electroplating, printing, plugging or spin-coating techniques.
- the conductive components 231 are made of conductive adhesives or electroplated metals, such as copper paste or silver glue.
- the passive components 24 are provided on the conductive components 231 .
- the passive components 24 are electrically connected to the conductive pads 21 a through the conductive components 231 .
- an active component (not shown) with a larger size can be provided on the wiring redistribution layer 222 .
- the present disclosure reduces the electrical connection path between the active component and the passive components 24 , and allows the voltage of the pins of the active component to be more stable.
- FIG. 3 a cross-sectional view of a package substrate 4 according to a third embodiment of the present disclosure is shown.
- the third embodiment differs from the second embodiment in the locations and the electrical connection method of the passive components 24 .
- a plurality of holes 232 are formed in the insulating protective layer 23 at locations corresponding to a portion of the exposed conductive pads 21 a by using a fixed-depth mechanical drilling method or a laser drilling method. Then, the passive components 24 are soldered onto the conductive pads 21 a in the holes 232 by dispensing, such that the passive components 24 are in contact with and electrically connected to the conductive pads 21 a.
- the height of the package substrate 4 can be reduced to facilitate product thinning.
- the present disclosure reduces the electrical connection path between the active component and the passive components 24 , and allows the voltage of the pins of the active component to be more stable.
- the wiring redistribution layer 222 of the interposer 22 is used for at least a active component such as a semiconductor chip (not shown) to be disposed, and packaging process is performed to form a semiconductor package.
- At least a passive component 24 ′ can be buried in the substrate 20 and electrically connected to the wirings 200 , as shown by the package substrate 4 ′ in FIG. 4 .
- the bottom surface 20 b of the substrate 20 of the present disclosure may also have conductive pads 2 lb for electrical connection to other electrical devices, such as circuit boards or package structures.
- a coreless substrate 20 is used for illustrating the various embodiments described above, a substrate with a core layer can also be applied in the package substrates of the present disclosure, and is deemed to be within the range of the claims of the present disclosure.
- the interposer 22 is integrated with the passive components 24 , so when an active component is provided on the interposer 22 , the distance between the active component and the passive components 24 is reduced, i.e., the electrical connection path between the active component and the passive components 24 is shortened. Therefore, the voltage of the pins of the active component can be more stable, and the electrical performance of the final electronic product is enhanced.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced.
Description
- This application claims priority to Taiwanese Patent Application No. 101135246, filed on Sep. 26, 2012.
- 1. Technical Field
- The present disclosure relates to package substrates and methods of fabricating the same, and relates to a package substrate having an embedded interposer and a method of fabricating the same.
- 2. Description of Related Art
- With the rapid development of the electronics industry, electronic products are becoming more and more compact, and the directions for research and development of their functions are moving towards high performance, multi-function, and high speed, resulting in increasing wiring density of semiconductor chips in the scale of nanometer. Therefore, package substrates for carrying the chips (such as flip-chip carriers) can no longer meet the demands for high wiring density of the semiconductor chips, thus a so-called 3D-SiP (System-in-package) packaging process is developed in the industry.
- The present disclosure provides a package substrate that integrates an interposer and passive components. The package substrate may include: a substrate with wirings, a first surface and a second surface opposing the first surface, the first surface including a plurality of conductive pads; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in the insulating protective layer and electrically connected to the substrate, the interposer including a plurality of penetrating conductive vias and a wiring redistribution layer exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate.
- The present disclosure can be more fully understood by reading the following detailed description of the embodiments, with reference made to the accompanying drawings, wherein:
-
FIG. 1 is a cross-sectional view of a package substrate according to a first embodiment of the present disclosure; -
FIGS. 2A to 2C are cross-sectional views of a package substrate according to a second embodiment of the present disclosure; -
FIG. 3 is a cross-sectional view of a package substrate according to a third embodiment of the present disclosure; and -
FIG. 4 is a cross-sectional view of a package substrate according to a fourth embodiment of the present disclosure. - In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a through understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
- It should be noted that the structures, proportions, sizes and the like shown in the attached drawings are to be considered only in conjunction with the contents of this specification to facilitate understanding and reading of those skilled in the art, and are not intended to limit the scope of present disclosure, thus they do not hold any real technically significance, and any changes or modifications in the structures, the proportions, the sizes and the like should fall within the scope of the technical contents disclosed in the present disclosure as long as they do not affect the effects and the objectives achieved by the present disclosure. Meanwhile, terms such as “on”, “top”, “bottom”, “surrounding”, “above”, “one” or “a” used in this specification are used for ease of illustration only, and not to limit the scope of the present disclosure, any changes or modifications of the relative relationships of elements are therefore to be construed as with the scope of the present disclosure as long as there is no changes to the technical contents.
- “Conductive vias” as mentioned herein refers to conductive components formed on a substrate, for example, the interposer herein. As shown in the diagrams, the shape of the conductive vias can be columnar.
- First Embodiment
- Referring to
FIG. 1 , a cross-sectional view of apackage substrate 2 according to a first embodiment of the present disclosure is shown. - A
substrate 20 havingwirings 200, a top surface (can be regarded as a first surface) 20 a and a bottom surface (can be regarded as a second surface) 20 b is provided. In an embodiment, thesubstrate 20 is a multilayer interconnect base plate. Thetop surface 20 a has a plurality ofconductive pads 21 a. Aninterposer 22 and an insulatingprotective layer 23 are formed on thetop surface 20 a. Theinterposer 22 is embedded into the insulatingprotective layer 23 and exposed from the surface of theinsulating protection layer 23. A plurality ofpassive components 24 are provided on theinterposer 22. - In an embodiment, the
interposer 22 is a silicon interposer and has a plurality of penetratingconductive vias 221 and a wiring redistribution layer (RDL) 222 exposed from the insulatingprotective layer 23. The bottom ends of theconductive vias 221 are each connected toconductive pads 21 a to electrically connect with thewirings 200, and thepassive components 24 are arranged on thewiring redistribution layer 222 to be electrically connected with theinterposer 22. - By disposing the
passive components 24 on thewiring redistribution layer 222, when an active component (not shown) such as a semiconductor chip is provided on thewiring redistribution layer 222, the active component can be assembled in a way that it is closest to thepassive components 24, thereby reducing the distance between the active component and thepassive components 24. - Signals are transmitted to the
substrate 20 through thewiring redistribution layer 222 and thepassive components 24 connected in series, and theconductive vias 221, so that the electrical connection path between the active component and thepassive components 24 is made shortest. As a result, the pins of the active component have stable voltage. - Second Embodiment
- Referring to
FIGS. 2A to 2C , cross-sectional views of apackage substrate 3 according to a second embodiment of the present disclosure are shown. The second embodiment differs from the first embodiment in the locations and the electrical connection method of thepassive components 24. - As shown in
FIG. 2A , a plurality ofholes 230 are formed in the insulatingprotective layer 23 at locations corresponding to a portion of the exposedconductive pads 21 a by using a fixed-depth mechanical drilling method or a laser drilling method. - As shown in
FIG. 2B ,conductive components 231 such as columns are formed in theholes 230 by electroplating, printing, plugging or spin-coating techniques. - In an embodiment, the
conductive components 231 are made of conductive adhesives or electroplated metals, such as copper paste or silver glue. - As shown in
FIG. 2C , thepassive components 24 are provided on theconductive components 231. Thepassive components 24 are electrically connected to theconductive pads 21 a through theconductive components 231. - In an embodiment, by providing the
passive components 24 on the insulatingprotective layer 23, an active component (not shown) with a larger size can be provided on thewiring redistribution layer 222. The present disclosure reduces the electrical connection path between the active component and thepassive components 24, and allows the voltage of the pins of the active component to be more stable. - Third Embodiment
- Referring to
FIG. 3 , a cross-sectional view of apackage substrate 4 according to a third embodiment of the present disclosure is shown. The third embodiment differs from the second embodiment in the locations and the electrical connection method of thepassive components 24. - As shown in
FIG. 3 , a plurality ofholes 232 are formed in the insulatingprotective layer 23 at locations corresponding to a portion of the exposedconductive pads 21 a by using a fixed-depth mechanical drilling method or a laser drilling method. Then, thepassive components 24 are soldered onto theconductive pads 21 a in theholes 232 by dispensing, such that thepassive components 24 are in contact with and electrically connected to theconductive pads 21 a. - In an embodiment, by embedding the
passive component 24 in the insulatingprotective layer 23, the height of thepackage substrate 4 can be reduced to facilitate product thinning. - Furthermore, when an active component is provided on the
wiring redistribution layer 222, the present disclosure reduces the electrical connection path between the active component and thepassive components 24, and allows the voltage of the pins of the active component to be more stable. - It should be noted that in the
package substrate wiring redistribution layer 222 of theinterposer 22 is used for at least a active component such as a semiconductor chip (not shown) to be disposed, and packaging process is performed to form a semiconductor package. - In the production of the
substrate 20, at least apassive component 24′ can be buried in thesubstrate 20 and electrically connected to thewirings 200, as shown by thepackage substrate 4′ inFIG. 4 . - In addition, the
bottom surface 20 b of thesubstrate 20 of the present disclosure may also haveconductive pads 2 lb for electrical connection to other electrical devices, such as circuit boards or package structures. - A
coreless substrate 20 is used for illustrating the various embodiments described above, a substrate with a core layer can also be applied in the package substrates of the present disclosure, and is deemed to be within the range of the claims of the present disclosure. - In summary, in the
package substrate interposer 22 is integrated with thepassive components 24, so when an active component is provided on theinterposer 22, the distance between the active component and thepassive components 24 is reduced, i.e., the electrical connection path between the active component and thepassive components 24 is shortened. Therefore, the voltage of the pins of the active component can be more stable, and the electrical performance of the final electronic product is enhanced. - It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
Claims (12)
1. A package substrate, comprising:
a substrate having a first surface and a second surface opposing to the first surface, the first surface including a plurality of conductive pads;
an insulating protective layer formed on the first surface of the substrate;
an interposer embedded in the insulating protective layer and electrically connected to the substrate, the interposer including a plurality of penetrating conductive vias and a wiring redistribution layer exposed from the insulating protective layer; and
at least a passive component provided on the first surface of the substrate.
2. The package substrate of claim 1 , wherein the at least a passive component is provided on the wiring redistribution layer and electrically connected to the interposer.
3. The package substrate of claim 1 , wherein the at least a passive component is provided on the insulating protective layer and electrically connected to the conductive pads through a plurality of conductive components formed in the insulating protective layer.
4. The package substrate of claim 3 , wherein the conductive components are made of conductive adhesive or electroplated metal.
5. The package substrate of claim 3 , wherein the conductive components are in the shape of a column.
6. The package substrate of claim 1 , wherein the insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least a passive component is provided on the conductive pad exposed from the opening.
7. The package substrate of claim 6 , further comprising at least another passive component embedded in the substrate.
8. A method of fabricating a package substrate, comprising:
providing a substrate having a first surface and a second surface opposing the first surface, wherein on the first surface a plurality of conductive pads and an insulating protective layer are formed, and an interposer is embedded in the insulating protective layer and electrically connected to the substrate, and includes a plurality of penetrating conductive vias and a wiring redistribution layer exposed from the insulating protective layer;
forming in the insulating protective layer at least an opening for exposing at least one of the conductive pads;
disposing a conductive component in each of the at least an opening; and
providing a passive component on the conductive component.
9. The method of claim 8 , wherein the conductive component is made of a conductive adhesive or an electroplated metal.
10. The method of claim 8 , wherein the conductive component is in the shape of a column.
11. A package substrate, comprising:
a substrate having a first surface and a second surface opposing the first surface, the first surface including a plurality of conductive pads;
an insulating protective layer formed on the first surface of the substrate;
an interposer embedded in the insulating protective layer and electrically connected to the substrate, the interposer including a plurality of penetrating conductive vias and a wiring redistribution layer exposed from the insulating protective layer; and
at least a passive component embedded in the substrate.
12. The package substrate of claim 11 , wherein the substrate includes at least a wiring through which the passive component is electrically connected to the interposer.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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US15/468,087 US10068847B2 (en) | 2012-09-26 | 2017-03-23 | Package substrate and method of fabricating the same |
US16/036,946 US10867907B2 (en) | 2012-09-26 | 2018-07-17 | Package substrate and method of fabricating the same |
US17/095,744 US11854961B2 (en) | 2012-09-26 | 2020-11-12 | Package substrate and method of fabricating the same and chip package structure |
US17/095,742 US11791256B2 (en) | 2012-09-26 | 2020-11-12 | Package substrate and method of fabricating the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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TW101135246A TWI483365B (en) | 2012-09-26 | 2012-09-26 | Package substrate and method of forming the same |
TW101135246 | 2012-09-26 |
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US15/468,087 Division US10068847B2 (en) | 2012-09-26 | 2017-03-23 | Package substrate and method of fabricating the same |
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US20140084413A1 true US20140084413A1 (en) | 2014-03-27 |
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US13/965,842 Abandoned US20140084413A1 (en) | 2012-09-26 | 2013-08-13 | Package substrate and method of fabricating the same |
US15/468,087 Active US10068847B2 (en) | 2012-09-26 | 2017-03-23 | Package substrate and method of fabricating the same |
US16/036,946 Active US10867907B2 (en) | 2012-09-26 | 2018-07-17 | Package substrate and method of fabricating the same |
US17/095,742 Active 2034-03-02 US11791256B2 (en) | 2012-09-26 | 2020-11-12 | Package substrate and method of fabricating the same |
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US15/468,087 Active US10068847B2 (en) | 2012-09-26 | 2017-03-23 | Package substrate and method of fabricating the same |
US16/036,946 Active US10867907B2 (en) | 2012-09-26 | 2018-07-17 | Package substrate and method of fabricating the same |
US17/095,742 Active 2034-03-02 US11791256B2 (en) | 2012-09-26 | 2020-11-12 | Package substrate and method of fabricating the same |
Country Status (3)
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US (4) | US20140084413A1 (en) |
CN (1) | CN103681588B (en) |
TW (1) | TWI483365B (en) |
Cited By (6)
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US20150115469A1 (en) * | 2013-10-25 | 2015-04-30 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate and method for manufacturing the same |
EP2978020A1 (en) * | 2014-07-25 | 2016-01-27 | Dyi-Chung Hu | Package substrate |
TWI550814B (en) * | 2015-07-31 | 2016-09-21 | 矽品精密工業股份有限公司 | Carrier body, package substrate, electronic package and method of manufacture thereof |
US20170047310A1 (en) * | 2015-08-13 | 2017-02-16 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the same |
CN107170730A (en) * | 2016-03-08 | 2017-09-15 | 胡迪群 | The encapsulation base material of layer is redistributed with two-sided fine rule |
US10687419B2 (en) * | 2017-06-13 | 2020-06-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI542263B (en) * | 2014-07-31 | 2016-07-11 | 恆勁科技股份有限公司 | Interposer substrate and a method for fabricating the same |
US10319607B2 (en) * | 2014-08-22 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with organic interposer |
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Also Published As
Publication number | Publication date |
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TWI483365B (en) | 2015-05-01 |
US20170194249A1 (en) | 2017-07-06 |
CN103681588B (en) | 2019-02-05 |
TW201413894A (en) | 2014-04-01 |
CN103681588A (en) | 2014-03-26 |
US10068847B2 (en) | 2018-09-04 |
US20210066189A1 (en) | 2021-03-04 |
US20180323143A1 (en) | 2018-11-08 |
US11791256B2 (en) | 2023-10-17 |
US10867907B2 (en) | 2020-12-15 |
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