CN1996584A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1996584A
CN1996584A CNA2006101562406A CN200610156240A CN1996584A CN 1996584 A CN1996584 A CN 1996584A CN A2006101562406 A CNA2006101562406 A CN A2006101562406A CN 200610156240 A CN200610156240 A CN 200610156240A CN 1996584 A CN1996584 A CN 1996584A
Authority
CN
China
Prior art keywords
lead
wire
semiconductor chip
bonding
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101562406A
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English (en)
Chinese (zh)
Inventor
岛贯好彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Publication of CN1996584A publication Critical patent/CN1996584A/zh
Pending legal-status Critical Current

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Classifications

    • H10W90/00—
    • H10P72/74—
    • H10W46/00—
    • H10W70/65—
    • H10W74/014—
    • H10W74/111—
    • H10W74/117—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H10P72/7418—
    • H10W46/101—
    • H10W46/607—
    • H10W72/015—
    • H10W72/0198—
    • H10W72/07141—
    • H10W72/075—
    • H10W72/07504—
    • H10W72/07511—
    • H10W72/07521—
    • H10W72/07533—
    • H10W72/07553—
    • H10W72/531—
    • H10W72/536—
    • H10W72/5363—
    • H10W72/5434—
    • H10W72/5445—
    • H10W72/5449—
    • H10W72/547—
    • H10W72/5473—
    • H10W72/5522—
    • H10W72/5525—
    • H10W72/59—
    • H10W72/884—
    • H10W72/932—
    • H10W74/00—
    • H10W90/28—
    • H10W90/732—
    • H10W90/734—
    • H10W90/752—
    • H10W90/754—
    • H10W99/00—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
CNA2006101562406A 2006-01-06 2006-12-27 半导体器件及其制造方法 Pending CN1996584A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006001027A JP4881620B2 (ja) 2006-01-06 2006-01-06 半導体装置及びその製造方法
JP2006001027 2006-01-06

Publications (1)

Publication Number Publication Date
CN1996584A true CN1996584A (zh) 2007-07-11

Family

ID=38231802

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101562406A Pending CN1996584A (zh) 2006-01-06 2006-12-27 半导体器件及其制造方法

Country Status (5)

Country Link
US (4) US7889513B2 (enExample)
JP (1) JP4881620B2 (enExample)
KR (1) KR101286874B1 (enExample)
CN (1) CN1996584A (enExample)
TW (3) TWI598971B (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367337A (zh) * 2012-03-30 2013-10-23 富士通天株式会社 半导体装置以及半导体装置的制造方法
CN104143518A (zh) * 2013-05-10 2014-11-12 瑞萨电子株式会社 制造半导体器件的方法以及半导体器件
CN105990167A (zh) * 2014-09-16 2016-10-05 株式会社东芝 导线键合装置及半导体装置
US11417625B2 (en) 2017-02-22 2022-08-16 Murata Manufacturing Co., Ltd. Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same

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JP4397408B2 (ja) * 2007-09-21 2010-01-13 株式会社新川 半導体装置及びワイヤボンディング方法
JP5205173B2 (ja) * 2008-08-08 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
TWM356216U (en) * 2008-12-12 2009-05-01 Kun Yuan Technology Co Ltd Memory chip packaging module
JP5411553B2 (ja) * 2009-03-31 2014-02-12 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
US8692370B2 (en) 2009-02-27 2014-04-08 Semiconductor Components Industries, Llc Semiconductor device with copper wire ball-bonded to electrode pad including buffer layer
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge
KR101746614B1 (ko) 2011-01-07 2017-06-27 삼성전자 주식회사 발광소자 패키지 및 그 제조방법
JP5893266B2 (ja) * 2011-05-13 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
TWI767243B (zh) * 2020-05-29 2022-06-11 矽品精密工業股份有限公司 電子封裝件
JP2023082337A (ja) * 2021-12-02 2023-06-14 ローム株式会社 半導体装置
TWI810963B (zh) * 2022-06-07 2023-08-01 華東科技股份有限公司 增進打線接合承受力之晶片封裝結構
CN116884862B (zh) * 2023-09-07 2023-11-24 江苏长晶科技股份有限公司 一种基于3d打印的凸点制作方法及芯片封装结构
WO2025219055A1 (en) * 2024-04-19 2025-10-23 Ams-Osram International Gmbh Optoelectronic package and method for manufacturing an optoelectronic package

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JPS5041818Y1 (enExample) * 1968-12-16 1975-11-27
JPS5041818U (enExample) * 1973-08-13 1975-04-28
JP3011510B2 (ja) * 1990-12-20 2000-02-21 株式会社東芝 相互連結回路基板を有する半導体装置およびその製造方法
JP3595386B2 (ja) * 1995-09-12 2004-12-02 田中電子工業株式会社 半導体装置
US5905639A (en) * 1997-09-29 1999-05-18 Raytheon Company Three-dimensional component stacking using high density multichip interconnect decals and three-bond daisy-chained wedge bonds
JP3662461B2 (ja) * 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
MY133357A (en) * 1999-06-30 2007-11-30 Hitachi Ltd A semiconductor device and a method of manufacturing the same
JP2001284370A (ja) * 2000-03-30 2001-10-12 Sanyo Electric Co Ltd 半導体装置の製造方法
JP4439090B2 (ja) * 2000-07-26 2010-03-24 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
JP4570809B2 (ja) * 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 積層型半導体装置及びその製造方法
JP3631120B2 (ja) 2000-09-28 2005-03-23 沖電気工業株式会社 半導体装置
US6867493B2 (en) * 2000-11-15 2005-03-15 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless multi-die carrier
JP4075306B2 (ja) * 2000-12-19 2008-04-16 日立電線株式会社 配線基板、ｌｇａ型半導体装置、及び配線基板の製造方法
US6894398B2 (en) * 2001-03-30 2005-05-17 Intel Corporation Insulated bond wire assembly for integrated circuits
US6787926B2 (en) * 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
JP3685779B2 (ja) 2002-08-27 2005-08-24 株式会社新川 ワイヤボンディング方法、ワイヤボンディング装置及びワイヤボンディングプログラム
JP2004214249A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
JP4615189B2 (ja) * 2003-01-29 2011-01-19 シャープ株式会社 半導体装置およびインターポーザチップ
JP3813135B2 (ja) * 2003-04-21 2006-08-23 株式会社新川 ワイヤボンディング方法
JP4308608B2 (ja) * 2003-08-28 2009-08-05 株式会社ルネサステクノロジ 半導体装置
JP4103796B2 (ja) * 2003-12-25 2008-06-18 沖電気工業株式会社 半導体チップパッケージ及びマルチチップパッケージ
KR100621547B1 (ko) * 2004-01-13 2006-09-14 삼성전자주식회사 멀티칩 패키지
KR100557540B1 (ko) * 2004-07-26 2006-03-03 삼성전기주식회사 Ｂｇａ 패키지 기판 및 그 제작 방법
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367337A (zh) * 2012-03-30 2013-10-23 富士通天株式会社 半导体装置以及半导体装置的制造方法
CN103367337B (zh) * 2012-03-30 2016-03-02 富士通天株式会社 半导体装置以及半导体装置的制造方法
CN104143518A (zh) * 2013-05-10 2014-11-12 瑞萨电子株式会社 制造半导体器件的方法以及半导体器件
CN105990167A (zh) * 2014-09-16 2016-10-05 株式会社东芝 导线键合装置及半导体装置
CN105990167B (zh) * 2014-09-16 2019-08-02 东芝存储器株式会社 导线键合装置及半导体装置
US11417625B2 (en) 2017-02-22 2022-08-16 Murata Manufacturing Co., Ltd. Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same

Also Published As

Publication number Publication date
TWI531016B (zh) 2016-04-21
TW201635402A (zh) 2016-10-01
US20070158392A1 (en) 2007-07-12
US20150348944A1 (en) 2015-12-03
TWI598971B (zh) 2017-09-11
TW200805526A (en) 2008-01-16
US9991229B2 (en) 2018-06-05
US20180277522A1 (en) 2018-09-27
KR20070074489A (ko) 2007-07-12
TWI404148B (zh) 2013-08-01
JP4881620B2 (ja) 2012-02-22
US20110159644A1 (en) 2011-06-30
JP2007184385A (ja) 2007-07-19
US7889513B2 (en) 2011-02-15
US10515934B2 (en) 2019-12-24
TW201347061A (zh) 2013-11-16
KR101286874B1 (ko) 2013-07-16

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