TW201347061A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201347061A
TW201347061A TW102125650A TW102125650A TW201347061A TW 201347061 A TW201347061 A TW 201347061A TW 102125650 A TW102125650 A TW 102125650A TW 102125650 A TW102125650 A TW 102125650A TW 201347061 A TW201347061 A TW 201347061A
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Taiwan
Prior art keywords
semiconductor wafer
main surface
wires
wire
pads
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TW102125650A
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English (en)
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TWI531016B (zh
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Yoshihiko Shimanuki
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Renesas Electronics Corp
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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  • Wire Bonding (AREA)

Abstract

本發明之目的係提供一種謀求抑制導線連接不良之半導體裝置。該半導體裝置具有:具有排列配置於主面3a之外周部之複數個引腳3h之封裝基板3、搭載於封裝基板3之主面3a的引腳列內側之半導體晶片1、連接半導體晶片1之接墊1c和基板之引腳3h之導線4、樹脂密封半導體晶片1及複數導線4之密封體、及設置於封裝基板3之背面之複數之焊料凸塊。進而,藉由將導線4之迴圈之頂點4b配置於導線連接部4a之外側,可增長引腳3h與半導體晶片1之接墊1c連接時之導線長度,其結果可謀求導線4之迴圈形狀之穩定,抑制導線連接不良。

Description

半導體裝置及其製造方法
本發明係關於一種半導體製造技術,特別係關於一種適用於抑制打線接合之連接不良之有效技術。
已知一種如下技術(例如,參照專利文獻1):於第1接合點形成縮頸部分後,一面放出第1預定量長度之導線一面使毛細管上升,並向第2接合點方向移動,形成第1打褶部分。使毛細管下降並向第2接合點之相反側方向移動,形成第2打褶部分。使毛細管上升,放出導線至第1打褶部分位於毛細管前端為止,於該狀態下使毛細管移動至第2接合點,形成導線迴圈。
又,已知一種技術(例如,參照專利文獻2),進行有以下步驟:於第1接合點連接導線之步驟、使毛細管稍微上升,進行第1反向動作之步驟、使毛細管上升,進行第2反向動作之步驟、及使毛細管上升,進行第3反向動作之步驟。進而,進行以下步驟:關閉接線板,將毛細管向第2接合點之相反方向水平移動之步驟、打開接線板,將毛細管向第2接合點方向水平移動之步驟、及將毛細管上升至第1接合點上方,放出導線,與第2接合點連接之步驟。
[專利文獻1]日本專利公開2004-87747號公報(圖2)
[專利文獻2]日本專利公開2004-319921號公報(圖1)
作為對應小型化之需求之半導體裝置之一例,已知有晶片尺寸與 半導體封裝(佈線基板)之尺寸幾乎相同之稱為CSP(晶片尺寸封裝)之半導體裝置。
上述CSP,因為半導體晶片之端部(邊緣)與佈線基板之端部(邊緣)之距離約為0.2~0.3mm窄(短),故形成於佈線基板之主面之導線連接用引腳(端子)與半導體晶片之端部(邊緣)之距離亦非常窄(短),約為0.1mm。因此,於打線接合步驟中,若藉由以與半導體晶片之電極連接之點為第1側、以與形成於佈線基板之主面之引腳連接之點為第2側之所謂正接合方式進行導線連接時,會發生導線無法進入毛細管與晶片端之間之現象。
如對此進行詳細說明,如圖27之比較例所示,毛細管18之一部分與從第1側向第2側下拉之導線4接觸。因此,如增長毛細管之從根部至前端之補充加工部分(L),可抑制與導線4之干涉,但由於於打線接合步驟中係藉由併用超音波之釘頭式接合方式進行,故如較細之L尺寸部分過長,因為毛細管18在較細部分會彎曲,因此,超音波很難傳至毛細管18之前端。
此外,正接合之情形,因為壓住第2側之導線時,導線4係從比第2側高之位置引出,故於圖27所示之A部,毛細管18之一部分易與導線4之間發生摩擦,毛細管18之一部分容易磨耗。
因此,如上述專利文獻1(日本專利公開2004-87747號公報)及上述專利文獻2(日本專利公開2004-319921號公報)之記載般,若藉由以與形成於佈線基板之主面之引腳連接之點為第1(第1接合)側、以與半導體晶片之電極連接之點為第2(第2接合)側之所謂逆接合方式進行導線連接,可抑制導線不良斷線。即,因為將導線從位於低位置之第1側沿垂直方向向上拉至與位於高位置之第2側大致相同高度,其後,水平方向移動毛細管與位於高位置之第2側連接,故於第1側之導線根部不會彎曲,其結果,可抑制導線不良斷線。
但是,如上所述,由於伴隨半導體裝置之小型化,形成於佈線基板之主面之引腳與半導體晶片之端部(邊緣)之距離亦非常窄,約為0.1mm,故若藉由逆接合方式進行導線連接,最後將導線倒向第2側時,因為導線之拉回之餘量不足,故會如圖28之比較例之小型封裝30所示,發生導線4與晶片端部接觸之現象。
換言之,因為來自卷線筒之送線速度與毛細管18之移動速度不對應,毛細管之移動速度比導線4之送線速度快,因此,導線供給力變小,形成之導線4短且不穩定,從而發生晶片端部短路,產生導線連接不良之問題。特別係於半導體晶片1之主面1a之端部形成測試圖案時,亦有測試圖案與導線4短路之問題。
【發明內容】
本發明之目的在於提供一種可謀求抑制導線連接不良之技術。
本發明之上述及其它目的與新的特徵,從本詳細說明書之記述及附加圖式應可清楚。
對本申請案中所揭示之發明中具有代表性者之概要進行簡單說明如下。
即,本發明之半導體裝置係具有:具有沿主面之邊緣部分配置之複數端子之佈線基板;搭載於佈線基板主面之端子列內側之半導體晶片;及連接半導體晶片之電極與佈線基板之端子,且連接佈線基板側之端子作為第1接合、連接半導體晶片之電極作為第2接合之複數導線;上述導線之一部分係較上述端子之導線連接部配置於靠近上述邊緣部分側。
此外,本發明之半導體裝置之製造方法係具有以下步驟:於佈線基板上配置半導體晶片後,將導線之前端部連接於佈線基板之端子,其後使毛細管向遠離半導體晶片之方向移動,從上述端子拉出導線, 進而將毛細管配置於半導體晶片之電極上後,將上述導線之一部分連接於半導體晶片之電極;並且,以使導線之一部分較佈線基板之端子之導線連接部配置於靠近上述邊緣部分側之方式連接導線。
就藉由本申請案中所揭示之發明中具有代表性者所獲得之效果進行簡單說明如下。
藉由將導線之一部分較佈線基板之端子中之第1接合之導線連接部配置於外側,導線繞至外側後拉回,故可增長連接佈線基板之端子與半導體晶片之電極之導線長度。藉此,導線之拉回之餘量增加,導線送線速度可跟上毛細管之移動速度,從而可謀求導線之迴圈形狀之穩定性。其結果,可減少晶片端部與導線之短路,降低導線連接不良之發生,能夠謀求抑制導線連接不良。
1‧‧‧半導體晶片
1a‧‧‧主面
1b‧‧‧背面
1c‧‧‧接墊(電極)
2‧‧‧黏晶用薄膜
3‧‧‧封裝基板(佈線基板)
3a‧‧‧主面
3b‧‧‧背面
3c‧‧‧芯材
3d‧‧‧連接盤
3e‧‧‧貫穿孔
3f‧‧‧防焊膜
3g‧‧‧銅配線
3h‧‧‧引腳
3i‧‧‧開口部
3j‧‧‧供電線
4‧‧‧導線
4a‧‧‧導線連接部
4b‧‧‧迴圈之頂點
5‧‧‧一體化密封體
6‧‧‧密封體
7‧‧‧CSP(半導體裝置)
8‧‧‧焊料凸塊(外部端子)
9‧‧‧多件同時加工基板
10‧‧‧標記
11‧‧‧切割刀片
12‧‧‧切割帶
13‧‧‧中心線
14‧‧‧CSP(半導體裝置)
15‧‧‧第2導線(其它導線)
15a‧‧‧導線連接部
15b‧‧‧迴圈之頂點
16‧‧‧第3導線
17‧‧‧第2半導體晶片(其它半導體晶片)
17a‧‧‧主面
17b‧‧‧背面
17c‧‧‧接墊(電極)
18‧‧‧毛細管
19‧‧‧金凸塊
20‧‧‧樹脂成型模具
20a‧‧‧內腔
30‧‧‧小型封裝
圖1係透過密封體顯示本發明之實施形態1之半導體裝置之構造之一例之平面圖。
圖2係顯示圖1所示之半導體裝置之構造之一例之截面圖。
圖3係顯示圖2所示之A部之構造之部分放大截面圖。
圖4係顯示圖3所示之導線結合部之構造之一例之部分放大截面圖。
圖5係顯示圖4所示之打線時毛細管之移動軌跡之一例之截面圖。
圖6係顯示圖4所示之打線時毛細管之移動軌跡之一例之截面圖。
圖7係顯示圖4所示之打線時毛細管之移動軌跡之一例之截面圖。
圖8係顯示圖4所示之打線時毛細管之移動軌跡之一例之截面圖。
圖9係顯示裝配於圖1所示之半導體裝置之佈線基板之主面側之佈線圖案之一例之平面圖。
圖10係顯示圖9所示之佈線基板之背面側之佈線圖案之一例之背 面圖。
圖11係顯示圖9所示之佈線基板之構造之一例之截面圖。
圖12係顯示圖11所示之A部之構造之部分放大截面圖。
圖13係顯示圖1所示之半導體裝置之組裝中至樹脂鑄型為止之組裝之一例之製程流程圖。
圖14係顯示圖1所示之半導體裝置之組裝中樹脂鑄型後之組裝之一例之製程流程圖。
圖15係顯示圖1所示之半導體裝置之組裝中樹脂鑄型後之組裝之變形例之製程流程圖。
圖16係顯示本發明之實施形態1之變形例之佈線基板之主面側之佈線圖案之平面圖。
圖17係顯示圖16所示之佈線基板之背面之佈線圖案之背面圖。
圖18係顯示圖16所示之佈線基板之構造之截面圖。
圖19係顯示圖18所示之A部之構造之部分放大截面圖。
圖20係顯示本發明之實施形態1之其它變形例之佈線基板之主面側之佈線圖案之平面圖。
圖21係顯示圖20所示之佈線基板之構造之截面圖。
圖22係顯示圖21所示之A部之構造之部分放大截面圖。
圖23係透過密封體顯示本發明之實施形態2之半導體裝置之構造之一例之平面圖。
圖24係顯示圖23所示之半導體裝置之構造之一例之截面圖。
圖25係顯示圖24所示之A部之構造之部分放大截面圖。
圖26係顯示圖24所示之B部之構造之部分放大截面圖。
圖27係顯示比較例之打線時毛細管壓抵狀態之一例之部分放大截面圖。
圖28係顯示比較例之打線接合後之連接不良之狀態之截面圖。
於以下之實施形態中,除特別必要時原則上不重複同一或相同部分之說明。
進而,於以下實施形態中,為求方便且有其必要時分割成複數之部分或實施形態進行說明,但除特別指明外,彼等並非互無關係,係一方面為另一方面之一部分或全部之變形例、詳細、補充說明等之關係。
此外,於以下之實施形態中,言及要件之數量等(包括個數、數值、量、範圍等)時,除了特別指明及於原理上明顯限定於特定數量時外,並非限定於該特定數量,為特定數量以上或以下俱可。
以下就本發明之實施形態參照圖式加以詳細說明。再者,於用於說明實施形態之全圖中,對具有相同功能之構件使用相同之符號,省略其重複說明。
[實施形態1]
圖1係透過密封體顯示本發明之實施形態1之半導體裝置之構造之一例之平面圖;圖2係顯示圖1所示之半導體裝置之構造之一例之截面圖;圖3係顯示圖2所示之A部之構造之部分放大截面圖;圖4係顯示圖3所示之導線結合部之構造之一例之部分放大截面圖;圖5~圖8係顯示圖4所示之打線時之毛細管之移動軌跡之一例之截面圖。此外,圖9係顯示裝配於圖1所示之半導體裝置之佈線基板之主面側之佈線圖案之一例之平面圖;圖10係顯示圖9所示之佈線基板之背面側之佈線圖案之一例之背面圖;圖11係顯示圖9所示之佈線基板之構造之一例之截面圖;圖12係顯示圖11所示之A部之構造之部分放大截面圖。進而,圖13係顯示圖1所示之半導體裝置之組裝中之至樹脂鑄型為止之組裝之一例之製程流程圖;圖14係顯示圖1所示之半導體裝置之組裝中之樹脂鑄型後之組裝之一例之製程流程圖;圖15係顯示圖1所示之半導體裝置 之組裝中之樹脂鑄型後之組裝之變形例之製程流程圖。
此外,圖16係顯示本發明之實施形態1之變形例之佈線基板之主面側之佈線圖案之平面圖;圖17係顯示圖16所示之佈線基板之背面側之佈線圖案之背面圖;圖18係顯示圖16所示之佈線基板之構造之截面圖;圖19係顯示圖18所示之A部之構造之部分放大截面圖。進而,圖20係顯示本發明之實施形態1之其它變形例之佈線基板之主面側之佈線圖案之平面圖;圖21係顯示圖20所示之佈線基板之構造之截面圖;圖22係顯示圖21所示之A部之構造之部分放大截面圖。
本實施形態1之半導體裝置係於佈線基板上搭載半導體晶片1之樹脂密封型之小型半導體封裝,於本實施形態1中作為其之一例,以圖1~圖3所示之CSP7進行說明。
再者,CSP7係於佈線基板之背面3b成格子狀配置安裝有作為複數之外部端子之焊料凸塊8,因此,CSP7係BGA(球形陣列)型之半導體封裝。
使用圖1~圖3就CSP7之構造進行說明,其具有:具有主面3a、與主面3a相對之背面3b和排列配置於主面3a之外周部之複數之引腳(端子)3h之佈線基板之封裝基板3;搭載於封裝基板3之主面3a之引腳列之內側(複數之引腳3h之內側區域)且具有積體電路之半導體晶片1。此外,亦具有:電性連接作為半導體晶片1之電極之接墊1c與封裝基板3之引腳3h之導電性導線4;配置於封裝基板3之主面3a與半導體晶片1之間(事先黏貼於半導體晶片1之背面)之作為黏晶材料之黏晶用薄膜2;設置於封裝基板3之背面3b之複數之連接盤3d上之作為外部端子(外部連接用端子)之焊料凸塊8。進而,具有樹脂密封半導體晶片1及複數之導線4之密封體6,且於作為封裝基板3之主面3a之保護膜之防焊膜3f上,經由黏晶用薄膜2固定半導體晶片1。
再者,CSP7雖然係小型之半導體封裝,但半導體晶片1之大小與 封裝基板3之大小大致相同,只是封裝基板3稍微大一些。例如,如圖4所示,從半導體晶片1之端部至封裝基板3之端部之距離(T1)約為0.2~0.3mm,非常窄(短)。
因此,於封裝基板3之主面3a之外周部(邊緣部分)形成之導線連接用引腳3h與半導體晶片1之端部(邊緣)之距離(T2)約為0.1mm,亦非常窄(短)。
此處,於CSP7方面,如圖1及圖3所示,於封裝基板3之晶片外側之區域、即基板之外周部排列配置有複數之引腳3h,設置於半導體晶片1之主面1a之作為電極之接墊1c和與此對應之封裝基板3之引腳3h藉由金線等導電性導線4電性連接。
此時,於本實施形態1之CSP7中,如圖1所示,複數之導線4分別係將半導體晶片1之接墊1c和與此對應之封裝基板3之引腳3h電性連接,同時以連接基板側之引腳3h作為第1接合,另一方面,連接晶片側之接墊1c作為第2接合。
此處,上述第1接合係以毛細管18將藉由電噴燈於導線前端形成之球抵壓於端子而連接者,另一方面,上述第2接合係於第1接合後,從上述端子拉出導線4而將毛細管18配置於另一端子上,其後,以毛細管18對上述另一端子壓破導線4之一部分,而與該另一端子連接者。
於本實施形態1之CSP7中,上述第1接合係對封裝基板3之引腳3h進行、上述第2接合係對半導體晶片1之接墊1c進行。即,CSP7係於半導體晶片1之接墊1c與佈線基板3之引腳3h之連接中,進行藉由逆接合之打線接合而組裝者。
此係因為CSP7係半導體晶片1與佈線基板3之大小大致相同之小型之半導體封裝,係從晶片之端部至基板之端部之距離約為0.2~0.3mm非常窄(短)之構造,進而引腳3h與晶片端部之距離亦約為0.1mm非常窄(短),故於基板上之半導體晶片1之外側區域,作為第2接合,要 一邊滑動毛細管18一邊配置很困難。
即,將於導線連接時使毛細管18從引腳3h向上方移動而只能確保打線接合用之很窄區域之基板側作為第1接合、晶片側作為第2接合。
進而,於本實施形態1之CSP7中,如圖1所示,於封裝基板3之主面3a上,藉由逆接合而連接之各導線4之一部分,較引腳3h之第1接合之導線連接部4a配置(形成)於外側(朝向封裝基板3之外周部)。
具體言之,如圖4所示,作為導線4之一部分之迴圈之頂點4b配置於第1接合之導線連接部4a之外側。即,各導線4之迴圈之最高點(此處係4b)係配置於導線連接部4a之導線拉出方向之中心線13之外側(遠離半導體晶片1之方向)。
此處,使用圖5~圖8,就圖4所示之導線4之迴圈形狀之形成方法加以說明,首先於封裝基板3之引腳3h進行第1接合。即將導線4之形成球狀之前端如圖4、圖5所示,以毛細管18壓抵於封裝基板3之如圖4所示之引腳3h而連接。
然後,如圖6所示,使毛細管18向遠離半導體晶片1方向移動,將導線4從上述引腳3h拉出。即,使毛細管18向遠離半導體晶片1方向(朝向封裝基板3之外周部)之斜上方移動,將導線4從上述引腳3h向斜上方拉出。
然後,於預定處暫時停止毛細管18之移動,接著如圖7所示,使毛細管18向正上方(垂直向上)移動,將導線4向上方拉出。
然後,於導線4超過晶片高度處停止毛細管18向上方之移動,然後如圖8所示,使毛細管18於半導體晶片1之接墊1c上大致水平移動,於半導體晶片1之接墊1c上配置導線4。
然後,於接墊1c藉由毛細管18壓潰導線4之一部分,於半導體晶片1之接墊1c上連接導線4。由此,完成作為導線4與半導體晶片1之接墊1c之連接之第2接合,同時成為各導線4之迴圈之頂點4b配置於導線連 接部4a之外側之狀態。
再者,於半導體晶片1之接墊1c上預先形成有金凸塊(螺柱凸塊)19,於第2接合時,將導線4與接墊1c上之金凸塊19連接。此係於打線接合步驟中,於第2接合時,為將導線4成磨擦毛細管18狀壓抵於接墊1c(或引腳3h),必須事先較大地形成接墊1c之形狀,其增大量至少為毛細管18之滑走距離。但是,如本實施形態1之逆接合方式之情形,如欲較大地形成於半導體晶片1之主面上形成之接墊1c,則半導體晶片1之小型化變得困難。進而,如於半導體晶片1之主面上進行上述壓抵動作,藉由壓抵壓力向半導體晶片1傳遞應力,特別係半導體晶片1之厚度較小之晶片之抗彎強度亦較低,成為造成晶片斷裂之原因。因此,於進行第2接合前預先形成金凸塊19。因為金凸塊19與接墊1c相比硬度較低,即便微小之壓抵壓力亦可輕易壓緊導線4之一部分。進而,因為藉由於進行第1接合前事先形成金凸塊19,可事先明白進行第2接合時之接合點,故打線接合之坐標不變,可進行穩定之打線接合步驟。但是,因為如半導體晶片1之面積較大、半導體晶片1之厚度亦較厚,則晶片之抗彎強度亦較高,故於接墊1c上亦可不形成金凸塊19,此時,導線4直接與接墊1c連接。
其次,就圖9~圖12所示之於CSP7所組裝之封裝基板3之構造加以說明。
封裝基板3具有:芯材3c、形成於其主面3a及背面3b之複數之導體部、連接主面3a和背面3b之上述導體部之貫穿孔3e和覆蓋上述導體部之至少一部分之防焊膜3f。於作為封裝基板3之表面之主面3a上,如圖9所示在基板之外周部(邊緣部分)沿各邊設置有排成一列之複數之引腳3h。
再者,引腳3h分別經由銅配線3g與貫穿孔3e電性連接。此外,於各引腳3h上朝向各自之外側連接有供電線3j。
另一方面,於封裝基板3之背面3b上,如圖10所示成格子狀配置有複數之連接盤3d,於此等連接盤3d上連接有作為外部端子之焊料凸塊8(參照圖3)。此外,複數之連接盤3d分別與貫穿孔3e連接。
如此於封裝基板3之主面3a及背面3b上形成有引腳3h、銅配線3g、供電線3j、連接盤3d及貫穿孔3e等導體部,此等導體部係由例如銅合金(Cu)形成。此外,於複數之連接盤3d及引腳3h上,為提高與導電性導線4之連接強度而於銅合金上進行了Ni/Au、或Ni/Pd/Au等表面處理。
此外,於封裝基板3之主面3a及背面3b上,形成有如圖12所示之作為絕緣膜之防焊膜3f。再者,於主面3a上,於防焊膜3f之細長開口部3i(參照圖9),複數之引腳3h以排列狀態露出。另一方面,於背面3b,僅露出連接盤3d。即,防焊膜3f覆蓋引腳3h或連接盤3d以外之作為導體部之銅配線3g、供電線3j及貫穿孔3e等。
其次,就裝入CSP7之各種構成構件之材質等進行說明,半導體晶片1例如藉由矽等形成,其主面1a上形成有積體電路。進而,如圖1所示於半導體晶片1之主面1a之邊緣部分形成有作為複數之電極之接墊1c。此外,電性連接此接墊1c和配置於封裝基板3之主面3a之外周部(邊緣部分)之引腳3h之導電性導線4係例如金線等。
此外,半導體晶片1如圖2、圖3所示,其背面1b經由黏晶用薄膜2被固定於封裝基板3上,以主面1a朝上之狀態搭載於封裝基板3上。
再者,樹脂密封半導體晶片1及複數之導電性導線4之密封體6,例如係藉由熱硬化性環氧樹脂等形成。
其次,使用圖13及圖14所示之製程流程圖就本實施形態1之CSP7之製造方法進行說明。
首先,進行圖13之步驟S1所示之準備基板。此處,準備已區劃配置有形成複數之封裝基板3之區域之多件同時加工基板9。再者,準備於封裝基板3之形成區域,在各區域之外周部(邊緣部分)排列配置有複 數之引腳3h之基板。
然後,進行步驟S2所示之黏晶,於多件同時加工基板9上經由圖3所示之黏晶用薄膜2固定半導體晶片1。此時,黏晶用薄膜2例如係藉由切割將半導體晶片單片化時所使用之切割用帶狀構件之黏接層殘留於晶片背面者。
再者,於與封裝基板3對應之各區域,於各區域之外周部排列配置有複數之引腳3h,因此,半導體晶片1搭載於外周部之引腳列之內側。
然後,進行步驟S3所示之打線接合。此處,如圖3及圖4所示,藉由金線等導電性導線4電性連接半導體晶片1之主面1a之接墊1c和與此對應之多件同時加工基板9之封裝基板3之引腳3h。
此時,本實施形態1中,藉由逆接合方式以導線4連接基板之引腳3h和半導體晶片1之接墊1c。此外,於各導線4,以使作為導線4之一部分之迴圈之頂點4b配置於第1接合之導線連接部4a之外側之方式,進行導線接合。即,進行導線接合,使各導線4之迴圈之最高點配置於導線連接部4a之導線拉出方向之中心線13之外側(封裝基板3之外周部側)。
打線接合步驟中,首先,對多件同時加工基板9之封裝基板3之區域之引腳3h進行第1接合。即,如圖5所示,將導線4之形成為球狀之前端部以毛細管18抵壓於基板之如圖4所示之引腳3h而連接。
然後,如圖6所示,使毛細管18向遠離半導體晶片1之方向移動,從上述引腳3h拉出導線4。即,使毛細管18向遠離半導體晶片1之方向之斜上方移動,從上述引腳3h向斜上方拉出導線4。
然後,於預定處暫時停止毛細管18之移動,其後如圖7所示,使毛細管18向正上方(垂直向上)移動,從上方拉出導線4。
然後,於導線4超過晶片高度處停止毛細管18向上方之移動,其後,如圖8所示,使毛細管18在半導體晶片1之接墊1c上大致水平移動,將導線4配置於半導體晶片1之接墊1c上。
然後,於接墊1c藉由毛細管18壓潰導線4之一部分,將導線4連接於半導體晶片1之接墊1c上。藉此,完成導線4與半導體晶片1之接墊1c之連接之第2接合,同時成為各導線4之迴圈之頂點4b配置於導線連接部4a外側之狀態。
再者,於半導體晶片1之接墊1c上,預先形成有金凸塊19,第2接合時,將導線4連接於接墊1c上之金凸塊19。但是,於接墊1c上亦可不形成金凸塊19,此時,將導線4直接連接於接墊1c。
然後,進行步驟S4所示之樹脂鑄型。此處,於多數同時加工基板9上,以於樹脂成型模具20之一個內腔20a全部覆蓋多件同時加工基板9上之複數區域(複數之封裝基板3之區域)之狀態進行樹脂密封,藉此,形成一體化密封體5。再者,形成一體化密封體5之密封用樹脂例如係熱硬化性環氧樹脂等。
然後,進行圖14之步驟S5所示之植球,如圖3所示,將焊料凸塊8連接於各連接盤3d。
然後,進行步驟S6所示之標記。此處,以雷射標記法等進行標記10,於一體化密封體5上作標記。再者,標記10亦可以例如噴墨標記法等進行。
然後,進行步驟S7所示之單片化。此處,於一體化密封體5之表面上黏貼切割帶12,於以切割帶12固定之狀態下藉由切割刀片11切斷,個體化成各CSP7。
藉此,如步驟S8所示,CSP7之組裝結束,製品完成。
再者,圖15係顯示藉由一體化密封之樹脂鑄型後之組裝之變形例之製程流程圖,此變形例之製程係於進行標記後進行植球者。
植球步驟,於封裝基板3之連接盤3d上塗上焊料後,藉由回焊處理形成焊料凸塊8。因此,於植球步驟中,亦由於此回焊處理會產生封裝基板3進一步彎曲之問題。於標記步驟用雷射標記法等進行標記,但 因為於封裝基板3之彎曲狀態下向一體化密封體5之表面垂直照射雷射變得困難,而發生一體化密封體5之表面未標記之標記不良之問題。
因此,於圖15所示之變形例中,於進行造成封裝基板3彎曲之主要原因之一之形成焊料凸塊8時之回焊處理前,先進行標記之步驟。藉此可抑制標記不良。
如據本實施形態1之半導體裝置及其製造方法,藉由將藉由逆接合連接之作為各導線之一部分之迴圈之頂點4b配置於封裝基板3之引腳3h中之第1接合之導線連接側4a之外側(封裝基板3之外周部側),因為係將導線4繞至外側後拉回,故可增長連接封裝基板3之引腳3h與半導體晶片1之接墊1c之導線長度。
藉此,導線4之拉回之餘量增加,送線速度可跟上毛細管18之移動速度,從而可謀求導線4之迴圈形狀之穩定。
其結果,可降低晶片端部與導線4之短路,從而減少導線連接不良之發生,可謀求抑制導線連接不良。
藉此,即使於半導體晶片1之主面1a之端部形成測試圖案時,亦可減少測試圖案與導線4之短路。
此外,因為藉由使導線4繞至外側,可加長由封裝基板端部至封裝基板3之端子(引腳3h)之距離,從而加長漏洩路程,故可確保吸濕不良之容許度。
此外,作為使導線4繞遠之方法,可增加迴圈之頂點4b之高度,形成較長導線長度,但此時,為使導線4之一部分不從密封體6之表面側露出,必須形成較厚之密封體6。為此,半導體裝置之薄型化變得困難。但是,於本實施形態1中,因為係使導線4繞至外側(半導體晶片1之相反側方向)向橫向膨脹,可防止導線4之一部分從密封體6之表面側露出。即,因為可於形成低迴圈之同時加長導線長度,故亦能對應CSP7之更薄型化。
進而,因為藉由低迴圈可加長導線長度,如半導體裝置之薄型化要求愈低,藉由以低迴圈形成導線4,可充分確保導線4之頂點4b至密封體6之表面之厚度。藉此,即使於密封體6之表面進行了雷射標記,亦可減低導線4從藉由雷射標記形成之溝槽露出、或藉由雷射光熔斷導線4之一部分之可能。
此外,於打線接合中,藉由採用逆接合方式,可避免於第2接合時將毛細管18極端地降至低側。藉此,可減少導線4無法進入毛細管18與半導體晶片1之端部之間之問題、或從第1側降至第2側之導線4與毛細管18之一部分接觸之問題、進而可降低毛細管18之前端與導線4之磨耗,從而可謀求增加毛細管18之使用壽命。
其次,就本實施形態1之變形例之封裝基板3進行說明。
圖16~圖19所示之變形例之封裝基板3,導體部之鍍敷係藉由無電鍍處理而形成者,為未形成有如圖9所示之封裝基板3之引腳3h之外側之供電線3j之構造。因此,形成於主面3a之防焊膜3f被配置於引腳3h上之導線連接部4a之內側。
此外,圖20~22所示之變形例之封裝基板3,係於各引腳3h之外側形成有供電線3j,另一方面,係不形成覆蓋供電線3j之防焊膜3f而使供電線3j與引腳3h同時露出之構造者。
此係因為於CSP中,從半導體晶片1之端部至封裝基板3之端部之距離約為0.2~0.3mm非常窄,且防焊膜3f之位置精度為±0.05mm非常高,故考慮到於供電線3j上形成防焊膜3f時之位置偏移,未形成防焊膜3f而將供電線3j露出。
但是,將供電線3j露出時,雖能迴避防焊膜3f之位置偏移之問題,但有產生吸濕之影響之可能,因此於各引腳3h之外側形成供電線3j時,形成或不形成覆蓋供電線3j之防焊膜3f均可,但如能兼顧晶片端部至基板端部之距離而形成,則以形成為佳。
[實施形態2]
圖23係透過密封體顯示本發明之實施形態2之半導體裝置之構造之一例之平面圖;圖24係顯示圖23所示之半導體裝置之構造之一例之截面圖;圖25係顯示圖24所示之A部之構造之部分放大截面圖;圖26係顯示圖24所示之B部之構造之部分放大截面圖。
圖23~圖26所示之本實施形態2之半導體裝置,係於半導體晶片1上經由黏晶用薄膜2固定有作為其它半導體晶片之第2半導體晶片17者,係與實施形態1之CSP7同樣之樹脂密封型之小型之晶片組構造之CSP14。
即,如圖25及圖26所示,經由黏晶用薄膜2於封裝基板3之主面3a之防焊膜3f上,將第1層(下層側)之半導體晶片1之主面1a朝上以面朝上安裝,進而於其上將第2層(上層側)之半導體晶片17之主面17a朝上以面朝上安裝。此時,第2半導體晶片17之背面17b亦藉由黏晶用薄膜2固定於半導體晶片1之主面1a上。
此外,CSP14係與實施形態1之CSP7同樣之小型之半導體封裝。即,半導體晶片1之大小與封裝基板3之大小大致相同,封裝基板3稍大。例如,半導體晶片之端部至封裝基板3之端部之距離與CSP7同樣約為0.2~0.3mm,非常窄。
因此,如圖25及圖26所示,上下層兩層之晶片俱為藉由逆接合進行打線接合而組裝者。
再者,關於第1層之半導體晶片1之打線接合,與基板側之引腳3h之導線連接為第1接合,與半導體晶片1之接墊1c之導線連接為第2接合。此時,與實施形態1之CSP7同樣,作為各導線4之一部分之迴圈頂點4b被配置於導線連接部4a之外側。即,各導線4之迴圈之最高點(此處為4b)被配置於導線連接部4a之導線拉出方向之中心線13之外側。
進而,第2層之第2半導體晶片17之導線連接中,如圖26所示,關 於連接第1層之半導體晶片1之接墊1c與上層(第2層)之第2半導體晶片17之接墊17c之第2導線(其它導線)15,因為接墊1c與接墊17c之距離較短,故與導線4同樣,作為各第2導線15之一部分之迴圈之頂點15b被配置於導線連接部15a之外側。即,各第2導線15之迴圈之最高點(此處為15b)被配置於導線連接部15a之導線拉出方向之中心線13之外側。
再者,第2層之第2半導體晶片17之導線連接中,如圖25所示,關於連接封裝基板3之引腳3h與上層(第2層)之第2半導體晶片17之接墊17c之第3導線16,進行一般之逆接合。即,於封裝基板3之引腳3h與上層之第2半導體晶片17之接墊17c之導線連接中,因為引腳3h與接墊17c之距離較長,可形成長度較長之導線,故可謀求導線迴圈之形狀之穩定化。
因此,於第2層之第2半導體晶片17之導線連接中,只對連接第1層之半導體晶片1之接墊1c與第2層之半導體晶片17之接墊17c之打線接合進行將第2導線15之迴圈頂點15b配置於導線連接部15a之外側之導線連接。
於本實施形態2之CSP14中,亦藉由將作為各導線之一部分之迴圈之頂點4b、15b分別配置於第1接合之導線連接部4a、15a之外側,將導線4及第2導線15繞至外側後拉回,故可加長導線長度。
藉此,導線4及第2導線15之拉回之餘量增加,送線速度可跟上毛細管18之移動速度,從而可謀求導線4及第2導線15之各迴圈之形狀之穩定。
其結果,可減少晶片端部與導線4或第2導線15之短路,從而可減少導線連接不良之發生,謀求抑制導線連接不良。
關於本實施形態2之CSP14之其它構造及其它效果,因為與實施形態1之CSP7相同,故省略其重複說明。
以上,就本發明者所完成之發明根據發明之實施形態進行了具體 說明,但本發明並非限定於上述發明之實施形態,不言而喻,於不脫離其宗旨之範圍內可作各種變更。
例如,於上述實施形態1及2中,作為半導體裝置之一例,就BGA型之小型之半導體封裝(CSP7、CSP14)進行了說明,但上述半導體裝置亦可為LGA(平面柵格陣列)型或QFN(無引線四方平整封裝)型者。
又,關於半導體晶片1及第2半導體晶片17之固定,不限於黏晶用薄膜2,例如使用糊狀之接著材等固定亦可。
此外,關於植球步驟,不局限於於封裝基板3之連接盤3d塗抹焊料後,藉由回焊處理形成焊料凸塊8之方法,亦可使用事先形成球形狀,再轉印至連接盤3d之方法、或經由掩膜印刷焊料之方法。
[產業上之可利用性]
本發明適用於具有佈線基板之電子裝置及其製造技術。
1‧‧‧半導體晶片
1a‧‧‧主面
1b‧‧‧背面
1c‧‧‧接墊(電極)
2‧‧‧黏晶用薄膜
3‧‧‧封裝基板(佈線基板)
3a‧‧‧主面
3f‧‧‧防焊膜
3g‧‧‧銅配線
3h‧‧‧引腳
3i‧‧‧開口部
3j‧‧‧供電線
4‧‧‧導線
4a‧‧‧導線連接部
4b‧‧‧迴圈之頂點
13‧‧‧中心線
19‧‧‧金凸塊

Claims (8)

  1. 一種半導體裝置之製造方法,其包含以下步驟:(a)準備第一半導體晶片之步驟,該第一半導體晶片包括:平面形狀為矩形之第一主表面、與上述第一主表面為相對側之第一背表面、及以沿著上述第一主表面之第一主表面邊之方式而配置在上述第一主表面之複數個第一接墊;(b)層積第二半導體晶片之步驟,該第二半導體晶片包括:平面形狀為矩形之第二主表面、與上述第二主表面為相對側之第二背表面、及以沿著上述第二主表面之第二主表面邊之方式而設置在上述第二主表面之複數個第二接墊,且將該第二半導體晶片以位於比包含上述複數個第一接墊之端子列更靠近上述第一半導體晶片之內側且上述第二背表面係與上述第一半導體晶片之上述第一主表面對向之方式,層積於上述第一半導體晶片之上述第一主表面;(c)將上述第二半導體晶片之上述複數個第二接墊與上述第一半導體晶片之上述複數個第一接墊經由複數之第一導線而分別電性連接之步驟;及(d)以樹脂密封上述第一半導體晶片、上述第二半導體晶片及上述複數之第一導線,藉此形成密封體之步驟,該密封體包括位於上述第二半導體晶片之上述第二主表面側之表面;於此,將上述第一導線之第一部分與上述第一半導體晶片之上述第一接墊連接之後,將上述第一導線之與上述第一部分不同之第二部分與上述第二半導體晶片之上述第二接墊連接,藉此形成上述複數之第一導線之每一者,且 上述複數之第一導線之每一者係形成為使得上述複數之第一導線之每一者之一部分位於比上述第一導線之上述第一部分更靠近上述第一半導體晶片之上述第一主表面之上述第一主表面邊側處。
  2. 如請求項1之半導體裝置之製造方法,其中上述(c)步驟中係使用併用超音波之毛細管而進行。
  3. 如請求項1之半導體裝置之製造方法,其中於截面觀察下,上述複數之第一導線之每一者係以包含位於比上述第二半導體晶片之上述第二主表面更靠近上述密封體之上述表面側處之頂點部之方式,自上述第一半導體晶片之上述第一接墊朝向上述第二半導體晶片之上述第二接墊之方向而迴圈狀地形成,上述複數之第一導線之每一者係形成為使得上述頂點部位於比上述第一導線之上述第一部分更靠近上述第一半導體晶片之上述第一主表面之上述第一主表面邊側處。
  4. 一種半導體裝置之製造方法,其包含以下步驟:(a)準備佈線基板之步驟,該佈線基板包括:平面形狀為矩形之上表面、與上述上表面為相對側之下表面、及以沿著上述上表面之上表面邊之方式而配置在上述上表面之複數個端子;(b)搭載第一半導體晶片之步驟,該第一半導體晶片包括:平面形狀為矩形之第一主表面、與上述第一主表面為相對側之第一背表面、及以沿著上述第一主表面之第一主表面邊之方式而配置在上述第一主表面之複數個第一接墊,且將該第一半導體晶片以位於比包含上述複數個端子之端子列更靠近上述佈線基板之內側處且上述第一背表面與上述佈線基板的上述上表面對向之方式,搭載於上述佈線基板之上述上表面; (c)層積第二半導體晶片之步驟,該第二半導體晶片包括:平面形狀為矩形之第二主表面、與上述第二主表面為相對側之第二背表面、及以沿著上述第二主表面之第二主表面邊之方式而配置在上述第二主表面之複數個第二接墊,且將該第二半導體晶片以位於比包含上述複數個第一接墊之端子列更靠近上述第一半導體晶片之內側處且上述第二背表面係與上述第一半導體晶片之上述第一主表面對向之方式,層積於上述第一半導體晶片之上述第一主表面;(d)將上述第二半導體晶片之上述複數個第二接墊與上述第一半導體晶片之上述複數個第一接墊經由複數之第一導線而分別電性連接,並將上述第二半導體晶片之上述複數個第二接墊與上述佈線基板之上述複數個端子經由複數之第二導線而分別電性連接之步驟;及(e)以樹脂密封上述第一半導體晶片、上述第二半導體晶片、上述複數之第一導線及上述複數之第二導線,藉此形成密封體之步驟,該密封體包括位於上述第二半導體晶片之上述第二主表面側之表面;於此,將上述第一導線之第一部分與上述第一半導體晶片之上述第一接墊連接之後,將上述第一導線之與上述第一部分不同之第二部分與上述第二半導體晶片之上述第二接墊連接,藉此形成上述複數之第一導線之每一者,上述複數之第一導線之每一者係形成為使得上述複數之第一導線之每一者之一部分位於比上述第一導線之上述第一部分更靠近上述第一半導體晶片之上述第一主表面之上述第一主表面邊側處, 上述複數之第二導線之每一者係形成為使得上述複數之第二導線之每一者不包含配置於比上述第二導線中之與上述佈線基板之上述端子連接之部分更靠近上述佈線基板之上述上表面之上述上表面邊側處之部分。
  5. 如請求項4之半導體裝置之製造方法,其中上述(d)步驟中係使用併用超音波之毛細管而進行
  6. 如請求項4之半導體裝置之製造方法,其中於截面觀察下,上述複數之第一導線之每一者係以包含位於比上述第二半導體晶片之上述第二主表面更靠近上述密封體之上述表面側處之頂點部之方式,自上述第一半導體晶片之上述第一接墊朝向上述第二半導體晶片之上述第二接墊之方向而迴圈狀地形成,上述複數之第一導線之每一者係形成為使得上述頂點部位於比上述第一導線之上述第一部分更靠近上述第一半導體晶片之上述第一主表面之上述第一主表面邊側處。
  7. 一種半導體裝置,其特徵在於包含:第一半導體晶片,其包括平面形狀為矩形之第一主表面、與上述第一主表面為相對側之第一背表面、及以沿著上述第一主表面之第一主表面邊之方式而配置在上述第一主表面之複數個第一接墊,且該第一半導體晶片係以位於比包含上述複數個端子之端子列更靠近上述佈線基板之內側處且上述第一背表面係與上述佈線基板的上述上表面對向之方式,搭載於上述佈線基板之上述上表面;第二半導體晶片,其包括平面形狀為矩形之第二主表面、與上述第二主表面為相對側之第二背表面、及以沿著上述第二主表面之第二主表面邊之方式而配置在上述第二主表面之複數個第二 接墊,且該第二半導體晶片係以位於比包含上述複數個第一接墊之端子列要靠近上述第一半導體晶片之內側處且上述第二背表面係與上述第一半導體晶片之上述第一主表面對向之方式,層積於上述第一半導體晶片之上述第一主表面;複數之第一導線,其將上述第二半導體晶片之上述複數個第二接墊與上述第一半導體晶片之上述複數個第一接墊分別予以電性連接;及密封體,其包括位於上述第二半導體晶片之上述第二主表面側之表面,且密封上述第一半導體晶片、上述第二半導體晶片及上述複數之第一導線;且上述複數之第一導線之每一者係包含與上述第一半導體晶片之上述複數個第一接墊之各者連接之第一導線連接部;且上述複數之第一導線之每一者之一部分係配置於比上述第一導線連接部更靠近上述第一半導體晶片之上述第一主表面之上述第一主表面邊側處。
  8. 一種半導體裝置,其特徵在於包含:佈線基板,其包括平面形狀為矩形之上表面、與上述上表面為相對側之下表面、及以沿著上述上表面之上表面邊之方式而配置在上述上表面之複數個端子;第一半導體晶片,其包括平面形狀為矩形之第一主表面、與上述第一主表面為相對側之第一背表面、及以沿著上述第一主表面之第一主表面邊之方式而配置在上述第一主表面之複數個第一接墊,且該第一半導體晶片係以位於比包含上述複數個端子之端子列更靠近上述佈線基板之內側處且上述第一背表面係與上述佈線基板的上述上表面對向之方式,搭載於上述佈線基板之上述上表面; 第二半導體晶片,其包括平面形狀為矩形之第二主表面、與上述第二主表面為相對側之第二背表面、及以沿著上述第二主表面之第二主表面邊之方式而配置在上述第二主表面之複數個第二接墊,且該第二半導體晶片係以位於比包含上述複數個第一接墊之端子列更靠近上述第一半導體晶片之內側處且上述第二背表面係與上述第一半導體晶片之上述第一主表面對向之方式,層積於上述第一半導體晶片之上述第一主表面;複數之第一導線,其將上述第二半導體晶片之上述複數個第二接墊與上述第一半導體晶片之上述複數個第一接墊分別予以電性連接;複數之第二導線,其將上述第二半導體晶片之上述複數個第二接墊與上述佈線基板之上述複數個端子分別予以電性連接;及密封體,其包括位於上述第二半導體晶片之上述第二主表面側之表面,且密封上述第一半導體晶片、上述第二半導體晶片、上述複數之第一導線及上述複數之第二導線;且上述複數之第一導線之每一者係包含與上述第一半導體晶片之上述複數個第一接墊之各者連接之第一導線連接部;且上述複數之第一導線之每一者之一部分係配置於比上述第一導線連接部更靠近上述第一半導體晶片之上述第一主表面之上述第一主表面邊側處;上述複數之第二導線之每一者係包含與上述配線基板之上述複數個端子之各者連接之第二導線連接部;且上述複數之第二導線之每一者係不包含配置於比上述第二導線連接部更靠近上述佈線基板之上述上表面之上述上表面邊側處之部分。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4397408B2 (ja) * 2007-09-21 2010-01-13 株式会社新川 半導体装置及びワイヤボンディング方法
JP5205173B2 (ja) * 2008-08-08 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
TWM356216U (en) * 2008-12-12 2009-05-01 Kun Yuan Technology Co Ltd Memory chip packaging module
WO2010098500A1 (ja) 2009-02-27 2010-09-02 三洋電機株式会社 半導体装置及びその製造方法
JP5411553B2 (ja) * 2009-03-31 2014-02-12 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge
KR101746614B1 (ko) 2011-01-07 2017-06-27 삼성전자 주식회사 발광소자 패키지 및 그 제조방법
JP5893266B2 (ja) * 2011-05-13 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6227223B2 (ja) * 2012-03-30 2017-11-08 富士通テン株式会社 半導体装置、及び半導体装置の製造方法
JP2014220439A (ja) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP2016062962A (ja) * 2014-09-16 2016-04-25 株式会社東芝 ワイヤボンディング装置、及び半導体装置
JP2018137342A (ja) 2017-02-22 2018-08-30 株式会社村田製作所 半導体装置及びその製造方法
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
TWI767243B (zh) * 2020-05-29 2022-06-11 矽品精密工業股份有限公司 電子封裝件
CN116884862B (zh) * 2023-09-07 2023-11-24 江苏长晶科技股份有限公司 一种基于3d打印的凸点制作方法及芯片封装结构

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5041818Y1 (zh) * 1968-12-16 1975-11-27
JPS5041818U (zh) * 1973-08-13 1975-04-28
JP3011510B2 (ja) * 1990-12-20 2000-02-21 株式会社東芝 相互連結回路基板を有する半導体装置およびその製造方法
JP3595386B2 (ja) * 1995-09-12 2004-12-02 田中電子工業株式会社 半導体装置
US5905639A (en) * 1997-09-29 1999-05-18 Raytheon Company Three-dimensional component stacking using high density multichip interconnect decals and three-bond daisy-chained wedge bonds
JP3662461B2 (ja) * 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
MY133357A (en) * 1999-06-30 2007-11-30 Hitachi Ltd A semiconductor device and a method of manufacturing the same
JP2001284370A (ja) * 2000-03-30 2001-10-12 Sanyo Electric Co Ltd 半導体装置の製造方法
JP4439090B2 (ja) * 2000-07-26 2010-03-24 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
JP4570809B2 (ja) * 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 積層型半導体装置及びその製造方法
JP3631120B2 (ja) 2000-09-28 2005-03-23 沖電気工業株式会社 半導体装置
US6867493B2 (en) * 2000-11-15 2005-03-15 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless multi-die carrier
JP4075306B2 (ja) * 2000-12-19 2008-04-16 日立電線株式会社 配線基板、lga型半導体装置、及び配線基板の製造方法
US6894398B2 (en) * 2001-03-30 2005-05-17 Intel Corporation Insulated bond wire assembly for integrated circuits
US6787926B2 (en) * 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
JP3685779B2 (ja) 2002-08-27 2005-08-24 株式会社新川 ワイヤボンディング方法、ワイヤボンディング装置及びワイヤボンディングプログラム
JP2004214249A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
JP4615189B2 (ja) * 2003-01-29 2011-01-19 シャープ株式会社 半導体装置およびインターポーザチップ
JP3813135B2 (ja) * 2003-04-21 2006-08-23 株式会社新川 ワイヤボンディング方法
JP4308608B2 (ja) * 2003-08-28 2009-08-05 株式会社ルネサステクノロジ 半導体装置
JP4103796B2 (ja) * 2003-12-25 2008-06-18 沖電気工業株式会社 半導体チップパッケージ及びマルチチップパッケージ
KR100621547B1 (ko) * 2004-01-13 2006-09-14 삼성전자주식회사 멀티칩 패키지
KR100557540B1 (ko) * 2004-07-26 2006-03-03 삼성전기주식회사 Bga 패키지 기판 및 그 제작 방법
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module

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