KR101286874B1 - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

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Publication number
KR101286874B1
KR101286874B1 KR1020070001430A KR20070001430A KR101286874B1 KR 101286874 B1 KR101286874 B1 KR 101286874B1 KR 1020070001430 A KR1020070001430 A KR 1020070001430A KR 20070001430 A KR20070001430 A KR 20070001430A KR 101286874 B1 KR101286874 B1 KR 101286874B1
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South Korea
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semiconductor chip
main surface
wire
wires
wiring board
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Korean (ko)
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KR20070074489A (ko
Inventor
요시히꼬 시마누끼
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르네사스 일렉트로닉스 가부시키가이샤
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
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    • H10W74/00Encapsulations, e.g. protective coatings
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    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
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    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • HELECTRICITY
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    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H10P72/7418Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. a chip mounting substrate
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    • H10W46/601Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607Located on parts of packages, e.g. on encapsulations or on package substrates
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    • H10W72/015Manufacture or treatment of bond wires
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07141Means for applying energy, e.g. ovens or lasers
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    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07502Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
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    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07511Treating the bonding area before connecting, e.g. by applying flux or cleaning
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07521Aligning
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07531Techniques
    • H10W72/07532Compression bonding, e.g. thermocompression bonding
    • H10W72/07533Ultrasonic bonding, e.g. thermosonic bonding
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07553Controlling the environment, e.g. atmosphere composition or temperature changes in shapes
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    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5434Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
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    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5473Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
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    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W72/931Shapes of bond pads
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    • H10W90/28Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W99/00Subject matter not provided for in other groups of this subclass

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  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
KR1020070001430A 2006-01-06 2007-01-05 반도체 장치 및 그 제조 방법 Active KR101286874B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006001027A JP4881620B2 (ja) 2006-01-06 2006-01-06 半導体装置及びその製造方法
JPJP-P-2006-00001027 2006-01-06

Publications (2)

Publication Number Publication Date
KR20070074489A KR20070074489A (ko) 2007-07-12
KR101286874B1 true KR101286874B1 (ko) 2013-07-16

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US (4) US7889513B2 (enExample)
JP (1) JP4881620B2 (enExample)
KR (1) KR101286874B1 (enExample)
CN (1) CN1996584A (enExample)
TW (3) TWI531016B (enExample)

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JP4397408B2 (ja) * 2007-09-21 2010-01-13 株式会社新川 半導体装置及びワイヤボンディング方法
JP5205173B2 (ja) * 2008-08-08 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
TWM356216U (en) * 2008-12-12 2009-05-01 Kun Yuan Technology Co Ltd Memory chip packaging module
JP5411553B2 (ja) * 2009-03-31 2014-02-12 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
US8692370B2 (en) 2009-02-27 2014-04-08 Semiconductor Components Industries, Llc Semiconductor device with copper wire ball-bonded to electrode pad including buffer layer
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge
KR101746614B1 (ko) 2011-01-07 2017-06-27 삼성전자 주식회사 발광소자 패키지 및 그 제조방법
JP5893266B2 (ja) * 2011-05-13 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6227223B2 (ja) * 2012-03-30 2017-11-08 富士通テン株式会社 半導体装置、及び半導体装置の製造方法
JP2014220439A (ja) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP2016062962A (ja) * 2014-09-16 2016-04-25 株式会社東芝 ワイヤボンディング装置、及び半導体装置
JP2018137342A (ja) 2017-02-22 2018-08-30 株式会社村田製作所 半導体装置及びその製造方法
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
TWI767243B (zh) * 2020-05-29 2022-06-11 矽品精密工業股份有限公司 電子封裝件
JP2023082337A (ja) * 2021-12-02 2023-06-14 ローム株式会社 半導体装置
TWI810963B (zh) * 2022-06-07 2023-08-01 華東科技股份有限公司 增進打線接合承受力之晶片封裝結構
CN116884862B (zh) * 2023-09-07 2023-11-24 江苏长晶科技股份有限公司 一种基于3d打印的凸点制作方法及芯片封装结构
WO2025219055A1 (en) * 2024-04-19 2025-10-23 Ams-Osram International Gmbh Optoelectronic package and method for manufacturing an optoelectronic package

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JPS5041818U (enExample) * 1973-08-13 1975-04-28
JPH0982738A (ja) * 1995-09-12 1997-03-28 Tanaka Denshi Kogyo Kk 半導体装置
JP2000307057A (ja) 1999-02-17 2000-11-02 Sharp Corp 半導体装置、およびその製造方法
US20020047213A1 (en) 2000-09-28 2002-04-25 Mitsuru Komiyama Multi-chip package type semiconductor device

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US10515934B2 (en) 2019-12-24
CN1996584A (zh) 2007-07-11
KR20070074489A (ko) 2007-07-12
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