TWI810963B - 增進打線接合承受力之晶片封裝結構 - Google Patents

增進打線接合承受力之晶片封裝結構 Download PDF

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TWI810963B
TWI810963B TW111121071A TW111121071A TWI810963B TW I810963 B TWI810963 B TW I810963B TW 111121071 A TW111121071 A TW 111121071A TW 111121071 A TW111121071 A TW 111121071A TW I810963 B TWI810963 B TW I810963B
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layers
bumps
dielectric
layer
chip
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TW111121071A
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TW202349614A (zh
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于鴻祺
林俊榮
古瑞庭
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華東科技股份有限公司
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Priority to TW111121071A priority Critical patent/TWI810963B/zh
Priority to KR2020230001002U priority patent/KR20230002363U/ko
Priority to JP2023001934U priority patent/JP3243078U/ja
Priority to US18/206,593 priority patent/US20230395538A1/en
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Publication of TWI810963B publication Critical patent/TWI810963B/zh
Publication of TW202349614A publication Critical patent/TW202349614A/zh

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  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一種增進打線接合承受力之晶片封裝結構，其中該晶片封裝結構之至少一導接線路係具有一厚度的結構體，各該導接線路的厚度設定為4.5~20微米（µm），藉此增進各該導接線路的結構強度以承受來自打線接合（Wire Bonding）作業或形成一第一銲點時所產生的正壓力，使一晶片之至少一內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在該第一銲點的下方，有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加的問題，有利於降低製造端的成本。

Description

增進打線接合承受力之晶片封裝結構
本發明係一種晶片封裝結構，尤指一種增進打線接合承受力之晶片封裝結構。
在晶片封裝領域中，欲使晶片封裝與電子元件電性連結，可藉由打線接合(Wire Bonding)之技藝來實現，即藉一銲線以在晶片封裝結構上形成一銲點與電子元件上形成另一銲點，以使晶片封裝結構與電子元件電性連結在一起。然而，當在進行打線接合作業時，現有的晶片封裝結構承受來自打線接合作業或形成該銲點時所產生的正壓力，使晶片之內部線路因該正壓力而受到破壞，而使內部線路不容易或無法通過或安排在晶片內的各晶墊的下方，為此，製造端需重新安排晶片之內部線路的設計，進而導致製造端成本增加。
因此，一種有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加之問題的增進打線接合承受力之晶片封裝結構，為目前相關產業之迫切期待者。
本發明之主要目的在於提供一種增進打線接合承受力之晶片封裝結構，其中該晶片封裝結構之至少一導接線路係具有一厚度的結構體，各該導接線路的厚度設定為4.5~20微米(μm)，藉此增進各該導接線路的結構強度以承受來自打線接合(Wire Bonding)作業或形成一第一銲點時所產生的正壓 力，使一晶片之至少一內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在該第一銲點的下方，有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加的問題。
為達成上述目的，本發明提供一種增進打線接合承受力之晶片封裝結構，該晶片封裝結構包含一晶片、至少一第一介電層、至少一第一凸塊、至少一第一保護層、至少一第二介電層、至少一導接線路、至少一第二凸塊、至少一第二保護層及至少一防銲層；其中該晶片具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊(Die Pad)及至少一保護層，其中該晶片係由一晶圓上所分割下來形成；其中各該第一介電層具有一第二表面及至少一第一凹槽，各該第一介電層係對應地覆蓋設於該晶片之該第一表面上，且各該第一凹槽係與該晶片之各該晶墊位置對應；其中各該第一凸塊具有一第三表面，各該第一凸塊係設於各該第一介電層之各該第一凹槽內，且各該第一凸塊係電性連結地設於該晶片之各該晶墊上；其中各該第一保護層具有一第四表面，各該第一保護層係設於各該第一介電層之各該第一凹槽內，且各該第一保護層係電性連結地設於各該第一凸塊之該第三表面上；其中各該第二介電層具有一第五表面及至少一第二凹槽，各該第二介電層係對應地覆蓋設於各該第一介電層之該第二表面上，且各該第二凹槽係涵蓋該晶片之各該晶墊；其中各該導接線路具有一第六表面，各該導接線路係設於各該第二介電層之各該第二凹槽內，且各該導接線路係設於各該第一介電層之該第二表面上、及各該第一保護層之該第四表面上，其中各該導接線路與各該第一保護層電性連結；其中各該第二凸塊具有一第七表面及一環周緣，各該第二凸塊係電性連結地設於各該導接線路之該第六表面上；其中各該第二保護層具有一第八表面，各該第二保 護層係設於各該第二凸塊之該第七表面上、各該第二凸塊之該環周緣、及各該第二介電層之該第五表面上，且各該第二保護層與各該第二凸塊電性連結；其中各該防銲層具有至少一第一開口，各該防銲層係設於各該第二保護層之該第八表面上，且各該防銲層之各該第一開口供各該第二保護層對外露出，其中各該導接線路在各該第一開口區域對應形成至少一銲墊(Pad)以對外電性連結；其中當在進行打線接合(Wire Bonding)作業時，藉一銲線以在各該第二保護層上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝結構與該電子元件電性連結在一起；其中該晶片封裝結構的製造方法包含下列步驟：步驟S1：提供一晶圓，該晶圓上設有多個形成陣列排列之晶片，各該晶片具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊(Die Pad)及至少一保護層；步驟S2：在該晶片之該第一表面上設至少一第一介電層對應地覆蓋該第一表面，各該第一介電層具有一第二表面；步驟S3：在各該第一介電層上成型出至少一第一凹槽，且各該第一凹槽係與該晶片之各該晶墊位置對應；步驟S4：在各該第一介電層之各該第一凹槽內設至少一第一凸塊，且各該第一凸塊係電性連結地設於該晶片之各該晶墊上，各該第一凸塊具有一第三表面；步驟S5：在各該第一介電層之各該第一凹槽內設至少一第一保護層，且各該第一保護層係電性連結地設於各該第一凸塊之該第三表面上，各該第一保護層具有一第四表面；步驟S6：在各該第一介電層之該第二表面上設至少一第二介電層對應地覆蓋該第二表面，各該第二介電層具有一第五表面；步驟S7：在各該第二介電層上成型出至少一第二凹槽，且各該第二凹槽係涵蓋該晶片之各該晶墊；步驟S8：在各該第二介電層之各該第二凹槽內設至少一導接線路，且各該導接線路係設於各該第一介電層之該第二表面上、各該第一保護層之該第四表 面上、及各該第二介電層之該第五表面上，其中各該導接線路與各該第一保護層電性連結；步驟S9：將各該導接線路中多餘的部分以線路研磨之技藝移除，此時，各該導接線路具有一第六表面；步驟S10：在各該導接線路之該第六表面上設至少一第二凸塊與各該導接線路電性連結，各該第二凸塊具有一第七表面及一環周緣；步驟S11：在各該第二凸塊之該第七表面上設至少一第二保護層與各該第二凸塊電性連結，且各該第二保護層亦設於各該第二凸塊之該環周緣、及各該第二介電層之該第五表面上，各該第二保護層具有一第八表面；步驟S12：在各該第二保護層之該第八表面上設至少一防銲層；步驟S13：在各該防銲層上成型出至少一第一開口，各該防銲層之該第一開口供各該第二保護層對外露出，其中各該導接線路在各該第一開口區域對應形成至少一銲墊(Pad)以對外電性連結；步驟S14：將該晶圓上多個該晶片進行分割作業以從該晶圓上分割成各個獨立的該晶片封裝結構；及步驟S15：在各個獨立的該晶片封裝結構上進行打線接合，藉一銲線以在各該第二保護層上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝結構與該電子元件電性連結在一起；其中各該導接線路係具有一厚度的結構體，各該導接線路的厚度設定為4.5~20微米(μm)，藉此增進各該導接線路的結構強度以承受來自打線接合作業或形成該第一銲點時所產生的正壓力，使該晶片之各該內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在該第一銲點的下方，以利於降低製造端的成本。
在本發明另一較佳實施例中，各該導接線路的厚度設定進一步為4.5~5微米(μm)。
在本發明另一較佳實施例中，各該防銲層進一步具有一第九表面；其中該晶片封裝結構進一步包含至少一外護層，各該外護層具有一第二開口，各該第二開口與各該防銲層之各該第一開口相通；其中各該外護層係對應地覆蓋設於各該防銲層之該第九表面上，且各該外護層之各該第二開口供各該第二保護層對外露出。
在本發明另一較佳實施例中，由各該第一介電層、各該第一凸塊、各該第一保護層、各該第二介電層、各該導接線路、各該第二凸塊、各該第二保護層、各該防銲層及各該外護層所堆疊形成的總厚度為25微米(μm)。
在本發明另一較佳實施例中，在步驟S12之中，進一步在各該防銲層之一第九表面上設有至少一外護層對應地覆蓋設於各該防銲層之該第九表面上。
在本發明另一較佳實施例中，在步驟S13之中，進一步在各該防銲層上成型出各該第一開口的同時，連同各該外護層一同成型出至少一第二開口，其中各該第一開口與各該第二開口相通。
1:晶片封裝結構
10:晶片
10a:第一表面
11:晶墊
12:保護層
13:內部線路
20:第一介電層
20a:第二表面
21:第一凹槽
30:第一凸塊
30a:第三表面
40:第一保護層
40a:第四表面
50:第二介電層
50a:第五表面
51:第二凹槽
60:導接線路
60a:第六表面
61:銲墊
70:第二凸塊
70a:第七表面
70b:環周緣
80:第二保護層
80a:第八表面
81:第一銲點
90:防銲層
90a:第九表面
91:第一開口
100:外護層
101:第二開口
2:晶圓
3:銲線
4:電子元件
4a:第二銲點
圖1為本發明一實施例之側視剖面平面示意圖。
圖2為第一實施例之晶片係由晶圓上所分割之側視剖面平面示意圖。
圖3為本發明之晶片封裝結構之側視剖面平面示意圖。
圖4為本發明之晶片之側視剖面平面示意圖。
圖5為在圖4中之晶片上設第一介電層之示意圖。
圖6為在圖5中之第一介電層上成型出第一凹槽之示意圖。
圖7為在圖6中之第一凹槽內設第一凸塊之示意圖。
圖8為在圖7中之第一凹槽內設第一保護層之示意圖。
圖9為在圖8中之第一介電層之第二表面上設第二介電層之示意圖。
圖10為在圖9中之第二介電層上成型出第二凹槽之示意圖。
圖11為在圖10中之第二凹槽內設導接線路之示意圖。
圖12為在圖11中之導接線路中多餘的部分以線路研磨之技藝移除之示意圖。
圖13為在圖12中之導接線路之第六表面上設第二凸塊之示意圖。
圖14為在圖13中之第二凸塊上設第二保護層之示意圖。
圖15為在圖14中之第二保護層之第八表面上設防銲層之示意圖。
圖16為在圖15中之防銲層上成型出第一開口之示意圖。
圖17為在圖16中之防銲層上設外護層之示意圖。
圖18為本發明之內部線路的上視平面示意圖。
圖19為本發明之晶片封裝的上視平面示意圖。
圖20為本發明之第一介電層、第一凸塊、第一保護層、第二介電層、導接線路、第二凸塊、第二保護層、防銲層及外護層所堆疊形成的總厚度為25微米(μm)之側視剖面平面示意圖。
圖21為本發明之導接線路的厚度設定為4.5~20微米(μm)之側視剖面平面示意圖。
配合圖示，將本發明的結構及其技術特徵詳述如後，其中各圖示只用以說明本發明的結構關係及相關功能，因此各圖示中各元件的尺寸並非依實際比例畫製且非用以限制本發明。
參考圖1及3，本發明提供一種增進打線接合承受力之晶片封裝結構1，該晶片封裝結構1包含一晶片10、至少一第一介電層20、至少一第一凸塊30、至少一第一保護層40、至少一第二介電層50、至少一導接線路60、至少一第二凸塊70、至少一第二保護層80及至少一防銲層90。
該晶片10具有一第一表面10a及至少一內部線路13，該第一表面10a上設有至少一晶墊(Die Pad)11及至少一保護層12如圖3所示；其中該晶片10係由一晶圓2上所分割下來形成如圖2所示。
其中，各該內部線路13係包含13a陣列區(Array)、13b電路區(Circuitry area)或電路細胞元(Cell)(未圖示)但不限制如圖18及19所示。
各該第一介電層20具有一第二表面20a及至少一第一凹槽21，各該第一介電層20係對應地覆蓋設於該晶片10之該第一表面10a上，且各該第一凹槽21係與該晶片10之各該晶墊11位置對應如圖3所示。
各該第一凸塊30具有一第三表面30a，各該第一凸塊30係設於各該第一介電層20之各該第一凹槽21內，且各該第一凸塊30係電性連結地設於該晶片10之各該晶墊11上如圖3所示。
各該第一保護層40具有一第四表面40a，各該第一保護層40係設於各該第一介電層20之各該第一凹槽21內，且各該第一保護層40係電性連結地設於各該第一凸塊30之該第三表面30a上如圖3所示。
各該第二介電層50具有一第五表面50a及至少一第二凹槽51，各該第二介電層50係對應地覆蓋設於各該第一介電層20之該第二表面20a上，且各該第二凹槽51係涵蓋該晶片10之各該晶墊11如圖3所示。
各該導接線路60具有一第六表面60a，各該導接線路60係設於各該第二介電層50之各該第二凹槽51內，且各該導接線路60係設於各該第一介電層20之該第二表面20a上、及各該第一保護層40之該第四表面40a上，其中各該導接線路60與各該第一保護層40電性連結如圖3所示。
各該第二凸塊70具有一第七表面70a及一環周緣70b，各該第二凸塊70係電性連結地設於各該導接線路60之該第六表面60a上如圖3所示。
各該第二保護層80具有一第八表面80a，各該第二保護層80係設於各該第二凸塊70之該第七表面70a上、各該第二凸塊70之該環周緣70b、及各該第二介電層50之該第五表面50a上，且各該第二保護層80與各該第二凸塊70電性連結如圖3所示。
各該防銲層90具有至少一第一開口91，各該防銲層90係設於各該第二保護層80之該第八表面80a上，且各該防銲層90之各該第一開口91供各該第二保護層80對外露出如圖3所示，其中各該導接線路60在各該第一開口91區域對應形成至少一銲墊(Pad)61以對外電性連結。
其中，各該銲墊61係受到各該第二凸塊70及各該第二保護層80的保護。
當在進行打線接合(Wire Bonding)作業時(如圖1所示)，藉一銲線3以在各該第二保護層80上形成一第一銲點81與一電子元件4上形成一第二銲點4a，以使該晶片封裝結構1與該電子元件4電性連結在一起如圖1所示。
參考圖1、2、4至17，本發明之該晶片封裝結構1的製造方法包含下列步驟：
步驟S1：提供一晶圓2，該晶圓2上設有多個形成陣列排列之晶片10如圖2所示，各該晶片10具有一第一表面10a及至少一內部線路13，該第一表面10a上設有至少一晶墊(Die Pad)11及至少一保護層12如圖4所示。
步驟S2：在該晶片10之該第一表面10a上設至少一第一介電層20對應地覆蓋該第一表面10a，各該第一介電層20具有一第二表面20a如圖5所示。
步驟S3：在各該第一介電層20上成型出至少一第一凹槽21，且各該第一凹槽21係與該晶片10之各該晶墊11位置對應如圖6所示。
步驟S4：在各該第一介電層20之各該第一凹槽21內設至少一第一凸塊30，且各該第一凸塊30係電性連結地設於該晶片10之各該晶墊11上，各該第一凸塊30具有一第三表面30a如圖7所示。
步驟S5：在各該第一介電層20之各該第一凹槽21內設至少一第一保護層40，且各該第一保護層40係電性連結地設於各該第一凸塊30之該第三表面30a上，各該第一保護層40具有一第四表面40a如圖8所示。
步驟S6：在各該第一介電層20之該第二表面20a上設至少一第二介電層50對應地覆蓋該第二表面20a，各該第二介電層50具有一第五表面50a如圖9所示。
步驟S7：在各該第二介電層50上成型出至少一第二凹槽51，且各該第二凹槽51係涵蓋該晶片10之各該晶墊11如圖10所示。
步驟S8：在各該第二介電層50之各該第二凹槽51內設至少一導接線路60，且各該導接線路60係設於各該第一介電層20之該第二表面20a上、各該 第一保護層40之該第四表面40a上、及各該第二介電層50之該第五表面50a上，其中各該導接線路60與各該第一保護層40電性連結如圖11所示。
步驟S9：將各該導接線路60中多餘的部分以線路研磨之技藝移除，此時，各該導接線路60具有一第六表面60a如圖12所示。
步驟S10：在各該導接線路60之該第六表面60a上設至少一第二凸塊70與各該導接線路60電性連結，各該第二凸塊70具有一第七表面70a及一環周緣70b如圖13所示。
步驟S11：在各該第二凸塊70之該第七表面70a上設至少一第二保護層80與各該第二凸塊70電性連結，且各該第二保護層80亦設於各該第二凸塊70之該環周緣70b、及各該第二介電層50之該第五表面50a上，各該第二保護層80具有一第八表面80a如圖14所示。
步驟S12：在各該第二保護層80之該第八表面80a上設至少一防銲層90如圖15所示。
步驟S13：在各該防銲層90上成型出至少一第一開口91，各該防銲層90之該第一開口91供各該第二保護層80對外露出如圖16所示，其中各該導接線路60在各該第一開口91區域對應形成至少一銲墊(Pad)61以對外電性連結如圖16所示。
步驟S14：將該晶圓2上多個該晶片10進行分割作業以從該晶圓2上分割成各個獨立的該晶片封裝結構1如圖2所示。
步驟S15：在各個獨立的該晶片封裝結構1上進行打線接合(Wire Bonding)，藉一銲線3以在各該第二保護層80上形成一第一銲點81與一電子元 件4上形成一第二銲點4a，以使該晶片封裝結構1與該電子元件4電性連結在一起如圖1所示。
其中，各該導接線路60係具有一厚度的結構體，各該導接線路60的厚度設定為4.5~20微米(μm)，藉此增進各該導接線路60的結構強度以承受來自打線接合作業或形成該第一銲點81時所產生的正壓力N如圖1所示，使該晶片10之各該內部線路13不會因該正壓力N(如圖1所示)而受到破壞，而使各該內部線路13能容許通過或安排在該第一銲點81的下方如圖19所示。
其中，各該導接線路60的厚度設定進一步為4.5~5微米(μm)但不限制。
參考圖3，各該防銲層90進一步具有一第九表面90a但不限制；其中該晶片封裝結構1進一步包含至少一外護層100，各該外護層100具有一第二開口101，各該第二開口101與各該防銲層90之各該第一開口91相通；其中各該外護層100係對應地覆蓋設於各該防銲層90之該第九表面90a上，且各該外護層100之各該第二開口101供各該第二保護層80對外露出。
其中，由各該第一介電層20、各該第一凸塊30、各該第一保護層40、各該第二介電層50、各該導接線路60、各該第二凸塊70、各該第二保護層80、各該防銲層90及各該外護層100所堆疊形成的總厚度為25微米(μm)但不限制如圖20所示。
參考圖17，在步驟S12之中，進一步在各該防銲層90之一第九表面90a上設有至少一外護層100對應地覆蓋設於各該防銲層90之該第九表面90a上。
參考圖3，在步驟S13之中，進一步在各該防銲層90上成型出各該第一開口91的同時，連同各該外護層100一同成型出至少一第二開口101，其中各該第一開口91與各該第二開口101相通。
本發明的該晶片封裝結構1與現有的晶片封裝結構相較，具有以下優點：本發明的其中該晶片封裝結構1之各該導接線路60係具有一厚度的結構體，各該導接線路60的厚度設定為4.5~20微米(μm)如圖21所示，藉此增進各該導接線路60的結構強度以承受來自打線接合作業或形成該第一銲點81時所產生的正壓力N(如圖1所示)，使該晶片10之各該內部線路13不會因該正壓力N(如圖1所示)而受到破壞，而使各該內部線路13能容許通過或安排在該第一銲點81的下方如圖19所示，有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加的問題，有利於降低製造端的成本。
以上該僅為本發明的優選實施例，對本發明而言僅是說明性的，而非限制性的；本領域普通技術人員理解，在本發明權利要求所限定的精神和範圍內可對其進行許多改變，修改，甚至等效變更，但都將落入本發明的保護範圍內。
1:晶片封裝結構
10:晶片
10a:第一表面
11:晶墊
12:保護層
13:內部線路
20:第一介電層
20a:第二表面
21:第一凹槽
30:第一凸塊
30a:第三表面
40:第一保護層
40a:第四表面
50:第二介電層
50a:第五表面
51:第二凹槽
60:導接線路
60a:第六表面
61:銲墊
70:第二凸塊
70a:第七表面
70b:環周緣
80:第二保護層
80a:第八表面
81:第一銲點
90:防銲層
90a:第九表面
91:第一開口
100:外護層
101:第二開口
3:銲線
4:電子元件
4a:第二銲點

Claims (6)

  1. 一種增進打線接合承受力之晶片封裝結構，其包含：一晶片，其具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊(Die Pad)及至少一保護層；其中該晶片係由一晶圓上所分割下來形成；至少一第一介電層，各該第一介電層具有一第二表面及至少一第一凹槽，各該第一介電層係對應地覆蓋設於該晶片之該第一表面上，且各該第一凹槽係與該晶片之各該晶墊位置對應；至少一第一凸塊，各該第一凸塊具有一第三表面，各該第一凸塊係設於各該第一介電層之各該第一凹槽內，且各該第一凸塊係電性連結地設於該晶片之各該晶墊上；至少一第一保護層，各該第一保護層具有一第四表面，各該第一保護層係設於各該第一介電層之各該第一凹槽內，且各該第一保護層係電性連結地設於各該第一凸塊之該第三表面上；至少一第二介電層，各該第二介電層具有一第五表面及至少一第二凹槽，各該第二介電層係對應地覆蓋設於各該第一介電層之該第二表面上，且各該第二凹槽係涵蓋該晶片之各該晶墊；至少一導接線路，各該導接線路具有一第六表面，各該導接線路係設於各該第二介電層之各該第二凹槽內，且各該導接線路係設於各該第一介電層之該第二表面上、及各該第一保護層之該第四表面上，其中各該導接線路與各該第一保護層電性連結；至少一第二凸塊，各該第二凸塊具有一第七表面及一環周緣，各該第二凸塊係電性連結地設於各該導接線路之該第六表面上； 至少一第二保護層，各該第二保護層具有一第八表面，各該第二保護層係設於各該第二凸塊之該第七表面上、各該第二凸塊之該環周緣、及各該第二介電層之該第五表面上，且各該第二保護層與各該第二凸塊電性連結；及至少一防銲層，各該防銲層具有至少一第一開口，各該防銲層係設於各該第二保護層之該第八表面上，且各該防銲層之各該第一開口供各該第二保護層對外露出，其中各該導接線路在各該第一開口區域對應形成至少一銲墊(Pad)以對外電性連結；其中當在進行打線接合(Wire Bonding)作業時，藉一銲線以在各該第二保護層上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝結構與該電子元件電性連結在一起；其中該晶片封裝結構的製造方法包含下列步驟：步驟S1：提供一晶圓，該晶圓上設有多個形成陣列排列之晶片，各該晶片具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊(Die Pad)及至少一保護層；步驟S2：在該晶片之該第一表面上設至少一第一介電層對應地覆蓋該第一表面，各該第一介電層具有一第二表面；步驟S3：在各該第一介電層上成型出至少一第一凹槽，且各該第一凹槽係與該晶片之各該晶墊位置對應；步驟S4：在各該第一介電層之各該第一凹槽內設至少一第一凸塊，且各該第一凸塊係電性連結地設於該晶片之各該晶墊上，各該第一凸塊具有一第三表面；步驟S5：在各該第一介電層之各該第一凹槽內設至少一第一保護層，且各該第一保護層係電性連結地設於各該第一凸塊之該第三表面上，各該第一保護層具有一第四表面； 步驟S6：在各該第一介電層之該第二表面上設至少一第二介電層對應地覆蓋該第二表面，各該第二介電層具有一第五表面；步驟S7：在各該第二介電層上成型出至少一第二凹槽，且各該第二凹槽係涵蓋該晶片之各該晶墊；步驟S8：在各該第二介電層之各該第二凹槽內設至少一導接線路，且各該導接線路係設於各該第一介電層之該第二表面上、各該第一保護層之該第四表面上、及各該第二介電層之該第五表面上，其中各該導接線路與各該第一保護層電性連結；步驟S9：將各該導接線路中多餘的部分以線路研磨之技藝移除，此時，各該導接線路具有一第六表面；步驟S10：在各該導接線路之該第六表面上設至少一第二凸塊與各該導接線路電性連結，各該第二凸塊具有一第七表面及一環周緣；步驟S11：在各該第二凸塊之該第七表面上設至少一第二保護層與各該第二凸塊電性連結，且各該第二保護層亦設於各該第二凸塊之該環周緣、及各該第二介電層之該第五表面上，各該第二保護層具有一第八表面；步驟S12：在各該第二保護層之該第八表面上設至少一防銲層；步驟S13：在各該防銲層上成型出至少一第一開口，各該防銲層之該第一開口供各該第二保護層對外露出，其中各該導接線路在各該第一開口區域對應形成至少一銲墊(Pad)以對外電性連結；步驟S14：將該晶圓上多個該晶片進行分割作業以從該晶圓上分割成各個獨立的該晶片封裝結構；及步驟S15：在各個獨立的該晶片封裝結構上進行打線接合，藉一銲線以在各該第二保護層上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝結構與該電子元件電性連結在一起； 其中各該導接線路係具有一厚度的結構體，各該導接線路的厚度設定為4.5~20微米(μm)，藉此增進各該導接線路的結構強度以承受來自打線接合作業或形成該第一銲點時所產生的正壓力，使該晶片之各該內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在該第一銲點的下方。
  2. 如請求項1所述之晶片封裝結構，其中各該導接線路的厚度設定進一步為4.5~5微米(μm)。
  3. 如請求項1所述之晶片封裝結構，其中各該防銲層進一步具有一第九表面；其中該晶片封裝結構進一步包含至少一外護層，各該外護層具有一第二開口，各該第二開口與各該防銲層之各該第一開口相通；其中各該外護層係對應地覆蓋設於各該防銲層之該第九表面上，且各該外護層之各該第二開口供各該第二保護層對外露出。
  4. 如請求項3所述之晶片封裝結構，其中由各該第一介電層、各該第一凸塊、各該第一保護層、各該第二介電層、各該導接線路、各該第二凸塊、各該第二保護層、各該防銲層及各該外護層所堆疊形成的總厚度為25微米(μm)。
  5. 如請求項1所述之晶片封裝結構，其中在步驟S12之中，進一步在各該防銲層之一第九表面上設有至少一外護層對應地覆蓋設於各該防銲層之該第九表面上。
  6. 如請求項5所述之晶片封裝結構，其中在步驟S13之中，進一步在各該防銲層上成型出各該第一開口的同時，連同各該外護層一同成型出至少一第二開口，其中各該第一開口與各該第二開口相通。
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