CN103367337A - 半导体装置以及半导体装置的制造方法 - Google Patents
半导体装置以及半导体装置的制造方法 Download PDFInfo
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- CN103367337A CN103367337A CN201210211291XA CN201210211291A CN103367337A CN 103367337 A CN103367337 A CN 103367337A CN 201210211291X A CN201210211291X A CN 201210211291XA CN 201210211291 A CN201210211291 A CN 201210211291A CN 103367337 A CN103367337 A CN 103367337A
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Abstract
一种半导体装置以及半导体装置的制造方法,能抑制成本并提高传输性能。半导体装置具有:电路基板(11)、MMIC芯片(121)、传输线路(13a)~(13o)、第一引线(W1)~(W12)和第二引线(W13)~(W15)。MMIC芯片(121)设置在电路基板(11)上。传输线路(13a)~(13o)形成在电路基板(11)上且与MMIC芯片(121)连接。第一引线(W1)~(W12)是一端与MMIC芯片(121)的端子接合之后,另一端与传输线路(13a)~(13l)的端子接合的引线。第二引线(W13)~(W15)是一端与传输线路(13m)~(13o)的端子接合之后,另一端与MMIC芯片(121)的端子接合的引线。
Description
技术领域
本发明涉及一种半导体装置以及半导体装置的制造方法。
背景技术
一直以来,当制造毫米波雷达等时,使用高频模块作为电子部件。高频模块具有MMIC(单片微波集成电路:MonolithicMicrowave Integrated Circuit)等芯片以及用于配置和连接上述芯片的电路基板。图7为在现有技术中引线连接了电路基板101和MMIC芯片102的半导体装置100的剖视图。如图7所示,在以往的高频模块中,在电路基板101的平面部上形成了凹部(cavity),在其内部配置了MMIC芯片(斜线部)102。由于凹部的深度与MMIC的芯片高度大致相同,因此,基板101的接合面和芯片102的接合面成为大致相同的高度。由此,在基板101和芯片102之间能够较短地布线引线W101和W102。由于引线的长度对信号的传输速度或传输损耗产生影响,因此,为了提高传输性能,很重要的一点就是缩短电子部件的引线长度。
但是,为了形成凹部,需要在基板表面设置如芯片的表面积那么大的开口部,并且进行与芯片的高度相同的挖掘的工序。另外,在能够形成凹部的电路基板的制造中,大多会使用陶瓷,在这种情况下,制造成本会增加。特别是在树脂基板的情况下,由于需要很高的加工精确度,因此,会在基板的加工中耗费很多时间,该时间从反映到制造成本中的结果来看,成为导致高频模块、甚至是毫米波雷达的竞争力下降的主要原因。如上所述,为了缩短引线长度而将MMIC芯片配置在凹部内会伴随着很大的成本。
为了避免上述成本的增加,存在以下的方法,即,在基板上粘接MMIC芯片,用引线将该芯片和基板上的传输线路连接。利用该方法的话,虽然加工成本降低,但引线长度增大,其结果是可能阻碍高性能化。因此,为了缩短引线长度,通常在从芯片侧向基板上的传输线路侧布线的引线接合工序中,进行逆向(从线路侧到芯片侧的方向)的布线。这种接合方法被称为逆向接合(reverse bonding),一直以来主要用于使封装的高度变薄。
(现有技术文献)
(专利文献)
专利文献1:特开2007-184385号公报
(发明概要)
(发明要解决的技术问题)
但是,在上述接合技术中存在例如如下所示的问题。即,在逆向接合中,并不是基板上的线路侧而是芯片侧成为第二接合,因此,通过缩短引线长度而提高了传输性能,但另一方面,有时会产生因接合导致的芯片损坏或因探针痕导致的接合性降低的问题。作为解决这一问题的技术,虽然BSOB(球打线:Bond StitchOn Ball)很有效,但在BSOB的执行工序中需要新的加工时间。另外,还存在随着加工时间的增加而使生产节拍(tact)(每个产品的制造时间)增长的问题。
发明内容
本发明所公开的技术就是鉴于上述问题而实现的,其目的是提供一种能够抑制成本并提高传输性能的半导体装置以及半导体装置的制造方法。
(解决技术问题的手段)
为了解决上述课题并达到目的,本申请所公开的半导体装置在一个实施方式中具有基板、芯片、传输线路、第一引线以及第二引线。上述芯片设置在基板上。上述传输线路形成在上述基板上且与上述芯片电连接。上述第一引线是一端与上述芯片的端子进行接合之后,另一端与上述传输线路的端子进行了接合的引线。上述第二引线是一端与上述传输线路的端子进行接合之后,另一端与上述芯片的端子进行了接合的引线。
(发明效果)
根据本申请公开的半导体装置的一个实施方式,能够抑制成本并提高传输性能。
附图说明
图1是设置有混合了通常接合与逆向接合的接收用MMIC芯片的基板表面的局部放大图。
图2是设置有混合了通常接合与逆向接合的发送用MMIC芯片的基板表面的局部放大图。
图3是通过通常接合进行了引线连接的半导体装置的局部剖视图。
图4是通过逆向接合进行了引线连接的半导体装置的局部剖视图。
图5表示在基板上具有抗蚀剂的半导体装置通过通常接合进行引线连接的情况。
图6表示在基板上没有抗蚀剂的半导体装置通过逆向接合进行引线连接的情况。
图7是在现有技术中引线连接了MMIC芯片和电路基板的半导体装置的剖视图。
图中:
10 半导体装置
11 电路基板
12 MMIC芯片
12a 芯片焊盘
13a~13l、13p~13u 传输线路(通常接合)
13m~13o、13v~13x 传输线路(逆向接合)
15、16 导电粘接剂
17 抗蚀剂(堤坝)
20 接合装置
100 半导体装置
101 电路基板
102 MMIC芯片
121 接收用MMIC芯片
122 发送用MMIC芯片
141 芯片侧引线接合焊盘
142 传输线路侧引线接合焊盘
B1 球形接合
B2 柱状凸块(BSOB)
G1、G2、G3、G4、G5、G6 通常接合区域
R1、R2 逆向接合区域
W1~W15、W21~W29、W31、W32、W41、W42 引线
W101、W102 引线
具体实施方式
以下,参照附图对本申请所公开的半导体装置以及半导体装置的制造方法的实施例进行详细说明。另外,本申请所公开的半导体装置以及半导体装置的制造方法不局限于以下的实施例。
图1是设置有混合了通常接合与逆向接合的接收用MMIC芯片121的基板表面的局部放大图。如图1所示,在电路基板11的表面配置有接收用MMIC芯片121。另外,在电路基板11的表面形成了传输线路13a~13o,在这些线路之中,传输线路13a~13l经由焊盘上的端子与接收用MMIC芯片121进行了引线连接。另一方面,在传输线路13a~13o之中,传输线路13m~13o经由焊盘上的端子与接收用MMIC芯片121进行了引线连接。
电路基板11在同一基板上具有通常接合区域G1~G4和逆向接合区域R1。通常接合区域G1~G4内的引线W1~W12利用通常的接合将接收用MMIC芯片121和传输线路13a~13l分别电连接,逆向接合区域R1内的引线W13~W15利用逆向接合将接收用MMIC芯片121和传输线路13m~13o分别电连接。即,在接收用MMIC芯片121中混合了利用通常接合进行了引线连接的端子和利用逆向接合进行了引线连接的端子。
发送用MMIC芯片122也采用与接收用MMIC芯片121同样的构成。图2是设置有混合了通常接合与逆向接合的发送用MMIC芯片122的基板表面的局部放大图。如图2所示,在电路基板11上混合有实施了通常接合的区域G5和G6,以及实施了逆向接合的区域R2。在通常接合区域G5和G6中,发送用MMIC芯片122和传输线路13p~13u之间用引线W21~W26电连接,在逆向接合区域R2中,发送用MMIC芯片122和传输线路13v~13x之间用引线W27~W29电连接。
在接收侧和发送侧的任意一个的MMIC芯片中也根据被连接的端子的类别决定是否是逆向接合。例如,逆向接合区域R1和R2都是对用于取得发送时与接收时的同步的端子进行了引线连接的区域。这样一来,在用于连接涉及信号传输的端子的引线接合中,即使多少花费些成本或时间,但从提高传输性能的观点来看,也优选采用容易进行低损耗的高速传输的逆向接合。相比之下,在其他区域G1~G6内的引线接合中,由于进行逆向接合的优点少,因此,为了抑制加工所需成本或时间,优选进行通常的接合。
即,半导体装置10根据端子将第一接合分割开,或设为通常的芯片或设为线路,由此,从将性能以及成本都考虑到的观点来看,会实施更高效的接合。接合方法的选择,例如根据上述端子是否是因引线长度而对传输速度或传输损耗产生影响的端子来进行。特别是在上述端子是连接成为毫米波(例如76GHz毫米波)的传输路径的引线(通过毫米波的引线)的端子的情况下,选择逆向接合。
图3是通过通常接合进行了引线连接的半导体装置10的局部剖视图。如图3所示,在电路基板11中,在芯片侧和线路侧这两侧都设置引线接合用的焊盘141和142。在芯片侧的引线接合焊盘141的表面涂敷导电粘接剂15,MMIC芯片12通过导电粘接剂15被粘接在芯片侧引线接合焊盘141上。在MMIC芯片12的表面隔着芯片焊盘12a形成球形接合B1,引线W31从该球形接合B1向传输线路侧引线接合焊盘142延伸,由此,在传输线路上布线MMIC芯片12。
图4是通过逆向接合进行了引线连接的半导体装置10的局部剖视图。如图4所示,在电路基板11上,在芯片侧和线路侧这两侧都设置引线接合用的焊盘141和142。在芯片侧的引线接合焊盘141的表面涂敷导电粘接剂15,利用导电粘接剂15将MMIC芯片12粘接在引线接合焊盘141上。在引线接合焊盘142的表面形成球形接合B1,引线W32从该球形接合B1向芯片焊盘12a上的柱状凸块B2延伸,由此,在MMIC芯片12上布线传输线路。柱状凸块B2与通常的球形接合B1不同,是由BSOB形成的。
在图4中,引线W32从球形接合B1向柱状凸块B2以大致最短距离延伸,相比之下,在图3中,引线W31从球形接合B1暂时以垂直方向延伸,然后向传输线路侧引线接合焊盘142延伸。即,利用通常的接合所形成的引线W31不采取最短距离,因此,其引线长度变得比利用逆向接合所形成的引线W32长。因此,引线W31虽然容易接合,但与引线W32相比,信号的传输距离变长。其结果是,引线W31会形成易于产生传输损耗并且传输速度也低的传输路径。
接合装置20按照规定的程序对MMIC芯片12和传输线路侧焊盘142执行引线接合。图5表示在电路基板11上具有抗蚀剂17的半导体装置10通过通常接合进行引线连接的情况。在半导体装置10的制造时,为了缩短用于将引线的两端与端子连接的接合焊盘之间的直线距离,且提高MMIC芯片12的散热性,因此,使用热传导率高的导电性粘接剂16。导电粘接剂16由例如Ag环氧树脂生成。此时,需要作为芯片焊盘的芯片侧引线接合焊盘141以不会借助导电粘接剂16与相邻的图案142接触的方式来确保芯片侧焊盘141和传输线路侧焊盘142之间的绝缘性。一般来讲,如图5所示,由抗蚀剂17形成堤坝(高低差)来防止导电粘接剂16流出到传输线路侧。但是,在该制造方法中,如果考虑到抗蚀剂17的宽度或布线图案的偏差等,则在芯片侧焊盘141和传输线路侧焊盘142之间就需要至少0.1~0.3mm的间隔,缩短引线W41就变得很困难。
图6表示在电路基板11上没有抗蚀剂17的半导体装置10通过逆向接合进行引线连接的情况。在图6所示的半导体装置10中,使用稀释剂成分比导电粘接剂16少的导电粘接剂15,并且在比MMIC芯片12的背面的面积小的面积上涂敷导电粘接剂15。由此,会抑制导电粘接剂15向传输线路侧流出。因此,即使将焊盘的间隔配置得较窄,也能确保芯片和传输线路之间的绝缘性。其结果是,在无需对电路基板11进一步加工的情况下就能很容易地进一步缩短引线W42的长度。由于除去了抗蚀剂17,因此,能够实现与例如在电路基板上实施凹部加工的以往的实施方式相同的引线长度。
另外,在MMIC芯片12表面的接合中,能够使用例如引线接合法。在这种情况下,芯片焊盘12a和引线W42是经由使用BSOB形成的柱状凸块B2而电连接的。另外,在引线接合法中,利用短环路连接技术能够实现与形成凹部的情况相同的引线长度。另一方面,在MMIC芯片12的背面接合中,能够使用例如裸芯片接合法(die bond)。在这种情况下,通过涂敷导电粘接剂15,能够同时兼顾强度与散热性。另外,通过使用非圆角粘接技术,能够维持可靠性,并能够消除导电粘接剂15从芯片外形溢出。
如上所述,本实施例的半导体装置10采用在一个芯片内混合有两种方向的接合的构成。半导体装置10具有电路基板11、MMIC芯片12、传输线路13a~13x以及引线W1~W15、W21~W29、W31、W32、W41和W42。MMIC芯片12形成在电路基板11上。传输线路13a~13x形成在电路基板11上并与MMIC芯片12电连接。各引线W1~W12、W21~W26、W31和W41在一端与MMIC芯片12的端子接合之后,另一端与传输线路13a~13l和13p~13u的端子接合(通常接合)。各引线W13~W15、W27~W29、W32和W42在一端与传输线路13m~13o、13v~13x的端子接合之后,另一端与MMIC芯片12的端子接合(逆向接合)。
关于MMIC芯片12和传输线路13a~13x之间的引线接合,如果将所有的接合都设置为以芯片侧的端子为起点的接合(通常接合),则不需要BSOB,由此使生产节拍变短。然而,另一方面,引线变长,由此性能方面(速度或薄度)变差。相比之下,如果将所有的接合都设置为以传输线路侧的端子为起点的接合(逆向接合),则性能虽然提高,但因需要BSOB工序或短环路连接技术,所以生产节拍增长。因此,在本实施例中,采用了在一个芯片内使通常接合与逆向接合同时存在,从而实现兼顾低成本和高速传输的构成。换句话说,通过选择性使用逆向接合来进行两种接合,能够在不增加接合所需时间的情况下缩短涉及传输性能(传输的速度或质量)的引线长度。
在半导体装置10中,连接各引线W13~W15、W27~W29、W32和W42的端子可以是引线长度对传输速度或传输损耗产生影响的端子。
并不是半导体装置10内的所有端子都对传输速度或传输损耗产生影响,因此,从加工时间的方面来考虑,对所有的端子实施高性能的逆向接合会使效率变差。因此,进行逆向接合的端子和不进行逆向接合的端子的区分就变得很重要,在选择进行逆向接合的端子时,优选选择引线长度对半导体装置10的传输速度或损耗产生影响的端子。由此,能够实现维持半导体装置10的性能并抑制了成本且有效率的逆向接合。
在半导体装置10中,与各引线W13~W15、W27~W29、W32和W42连接的端子也可以是与天线波导管连接的端子。
在引线长度对传输速度或传输损耗产生影响的端子之中,特别是与天线波导管连接的端子的引线会形成从芯片到天线的波导路径,因此,对天线的增益或传输速度会产生更直接的影响。因此,半导体装置10通过在该端子的接合中使用逆向接合,从而能够维持天线的增益特性并确保高的传输性能。另外,通过对其他的端子使用通常接合,从而对于为了发挥高的传输性能而需要短的引线长度的端子能够精确(pinpoint)使用逆向接合。
在半导体装置10中,在电路基板11和MMIC芯片12之间还具有用于将MMIC芯片12固定在电路基板11上的导电粘接剂15,但在这种情况下,能够不需要用于防止流出的堤坝而单独通过导电粘接剂15,以粘接剂不会从芯片溢出的方式进行粘接。
以往,在电路基板11上设置了用于防止上述导电粘接剂15从芯片侧流出到传输线路侧的堤坝(抗蚀剂),但在本实施例中,导电粘接剂15存在于MMIC芯片12和电路基板11之间。因此,芯片和基板之间的导电粘接剂15不会从芯片背面向外流出。因此,本实施例的半导体装置10无需在基板上设置用于防止导电粘接剂15流出的堤坝(抗蚀剂)17,这样一来,能够缩短芯片和基板的端子之间的距离(引线长度)。即,半导体装置10在逆向接合时能够进一步缩短引线。其结果是,能够实现传输损耗少的高速的信号传输。
并且,半导体装置10的制造方法,包括半导体制造装置所执行的以下的各工序。在基板形成工序中,半导体装置10在电路基板11上形成用于连接MMIC芯片12的传输线路13a~13x。在芯片设置工序中,半导体装置10在电路基板11上设置MMIC芯片12。在接合方法选择工序中,半导体装置10根据进行引线连接的端子的功能或类别来选择上述通常接合与上述逆向接合中的任意一种接合。在接合工序中,半导体装置10按照每个端子执行所选择的接合。
本实施例的半导体装置10的进一步的效果,是能够容易地进行图案布线。即,在逆向接合中,如果焊盘之间的距离较长,则难以形成,因此,在进行逆向接合时,需要在某种程度上使芯片侧焊盘141和传输线路侧焊盘142的间隔变窄。因此,如果为了实现高速传输而将基板上的所有端子通过逆向接合进行引线连接,则存在能够用于图案布线的基板上的空间减少,会担心难以形成传输线路。但是,在本实施例的半导体装置10中,只针对将引线长度作为问题看待的端子进行基于逆向接合的引线连接。由此,在所有的接合数量之中,只有一部分成为逆向接合(例如,所有引线的20~30%的根数),半导体装置10能够留下很多焊盘间隔较宽的部分。由此,就变得容易在基板上确保空出的空间,通过在该空间上进行图案布线,从而能够容易地形成传输线路。其结果是,解决了上述的担忧。
另外,虽然在上述实施例中举例表示了在逆向接合中不在电路基板11上设置堤坝的方式(参照图6),但不局限于此,在通常接合中也同样能够采用不需要堤坝的构成。
另外,在制造半导体装置10时,与所进行的接合的种类无关,使制造装置按照端子配置的顺序进行引线接合,由此来实现加工处理的效率化。即,能够缩短为了进行接合的机械臂的移动距离,并能够降低加工所需时间或成本。不过,制造装置也可以对不会影响传输性能的所有端子进行通常接合,在此之后,对其余的端子进行逆向接合。另外,接合的顺序也可以与此相反。
(产业上的可利用性)
如上所述,本发明的半导体装置以及半导体装置的制造方法对于高速并且低成本的电子部件的生产很有用,特别适合用于制造安装在车辆上的毫米波雷达等。
Claims (5)
1.一种半导体装置,其特征为,具有:
基板上的芯片;
传输线路,其形成在上述基板上且与上述芯片连接;
第一引线,其一端与上述芯片的端子进行接合之后,另一端与上述传输线路的端子进行了接合;
第二引线,其一端与上述传输线路的端子进行接合之后,另一端与上述芯片的端子进行了接合。
2.根据权利要求1所述的半导体装置,其特征为,
连接上述第二引线的端子是引线长度会对传输速度或传输损耗产生影响的端子。
3.根据权利要求2所述的半导体装置,其特征为,
连接上述第二引线的端子是与天线波导管连接的端子。
4.根据权利要求1所述的半导体装置,其特征为,
在上述基板和上述芯片之间还具有用于将上述芯片固定在上述基板上的导电粘接剂,该导电粘接剂是以不从上述芯片的面积溢出的方式进行粘接的。
5.一种半导体装置的制造方法,其特征为,包括:
在基板上形成用于连接芯片的传输线路的工序;
在上述基板上设置上述芯片的工序;
根据进行引线连接的端子来选择第一接合和第二接合中任一种接合的工序,其中,上述第一接合是指:在将引线的一端与上述芯片的端子进行接合之后,将上述引线的另一端与上述传输线路的端子进行接合,上述第二接合是指:在将引线的一端与上述传输线路的端子进行接合之后,将上述引线的另一端与上述芯片的端子进行接合;以及
针对上述每个端子进行所选择的接合的工序。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4618879A (en) * | 1983-04-20 | 1986-10-21 | Fujitsu Limited | Semiconductor device having adjacent bonding wires extending at different angles |
JP2001015542A (ja) * | 1999-07-02 | 2001-01-19 | Sanken Electric Co Ltd | 半導体装置及びその製造方法 |
US20030205725A1 (en) * | 2000-07-26 | 2003-11-06 | Kenji Masumoto | Semiconductor device and its manufacturing method |
JP2004111677A (ja) * | 2002-09-19 | 2004-04-08 | Rohm Co Ltd | ワイヤボンディング方法 |
CN1996584A (zh) * | 2006-01-06 | 2007-07-11 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
CN101960608A (zh) * | 2008-03-11 | 2011-01-26 | 松下电器产业株式会社 | 半导体设备以及半导体设备的制造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61113243A (ja) * | 1984-11-07 | 1986-05-31 | Fuji Xerox Co Ltd | 混成集積回路の実装方法 |
TWI242275B (en) * | 2003-05-16 | 2005-10-21 | Via Tech Inc | Multi-column wire bonding structure and layout method for high-frequency IC |
JP2007088378A (ja) * | 2005-09-26 | 2007-04-05 | Mitsubishi Electric Corp | 半導体モールドパッケージ |
JP2009302180A (ja) * | 2008-06-11 | 2009-12-24 | Toshiba Corp | 半導体装置 |
JP5442424B2 (ja) * | 2009-12-25 | 2014-03-12 | 新光電気工業株式会社 | 半導体装置 |
-
2012
- 2012-03-30 JP JP2012082736A patent/JP6227223B2/ja not_active Expired - Fee Related
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4618879A (en) * | 1983-04-20 | 1986-10-21 | Fujitsu Limited | Semiconductor device having adjacent bonding wires extending at different angles |
JP2001015542A (ja) * | 1999-07-02 | 2001-01-19 | Sanken Electric Co Ltd | 半導体装置及びその製造方法 |
US20030205725A1 (en) * | 2000-07-26 | 2003-11-06 | Kenji Masumoto | Semiconductor device and its manufacturing method |
JP2004111677A (ja) * | 2002-09-19 | 2004-04-08 | Rohm Co Ltd | ワイヤボンディング方法 |
CN1996584A (zh) * | 2006-01-06 | 2007-07-11 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
CN101960608A (zh) * | 2008-03-11 | 2011-01-26 | 松下电器产业株式会社 | 半导体设备以及半导体设备的制造方法 |
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