CN1992345A - 包括双隧道氧化物层的闪存单元及其制造方法 - Google Patents
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Abstract
本发明公开了一种包括双隧道氧化物层的闪存单元及其制造方法。该闪存单元包括:隧道氧化物层,其包括在半导体衬底上具有第一厚度的第一隧道和具有第二厚度的第二隧道;电荷存储层,形成在隧道氧化物层上;绝缘层,形成在电荷存储层上;以及控制栅极,形成在绝缘层上,并供以驱动电源。第一隧道的第一厚度比第二隧道的第二厚度薄。
Description
技术领域
本发明涉及一种半导体器件。更具体地,本发明涉及一种闪存单元及其制造方法。
背景技术
一般而言,闪存是一种非易失性半导体存储器,其被设计用于执行可擦写可编程只读存储器(EPROM)的编程方法以及电可擦写可编程只读存储器(EEPROM)的擦写方法,并且闪存被恰当地命名为快闪EEPROM。闪存不仅可以在断电时保持已存储的信息,还可以自由地输入和输出信息,因此,近来闪存广泛地应用于数字电视、可携式数字摄像机、移动电话、数码相机、个人数字助理以及游戏机等等。
根据单元结构,通常闪存可分为堆叠栅极型和分离栅极型。其中,堆叠栅极型闪存具有这样的结构结构,即将用于存储电荷的浮置栅极和施加了驱动电源的控制栅极简单地堆叠的结构。
图1示意性地示出普通堆叠栅极型闪存的存储单元。参照图1,沿闪存的位线方向,在半导体衬底10上形成限定有源器件区的多个隔离层(未示出)。在相邻的隔离层之间的有源器件区上依次形成隧道氧化物层20、浮置栅极22、栅极间绝缘层24以及控制栅极26。在半导体衬底10的表面上形成源极和漏极扩散区14,其中,源极扩散区和漏极扩散区隔着浮置栅极22下的沟道区相互分开。
如图1所示,通过以沟道热电子注入模式将漏极电子注入浮置栅极,对堆叠栅极型闪存的存储单元进行编程,并且通过富雷-诺特海姆(FN,Fowler-Nordheim)隧穿机制将限制在浮置栅极中的电子发射出来,以对该闪存的存储单元进行擦写。图2示出普通NOR型闪存单元的栅极电压VG-电流Id特性。在擦写状态下,浮置栅极有多余的空穴,这样,晶体管的特性变为损耗型,如同虚线所示的曲线(a)。因此,存储器单元的特性变为沟道增强型,如同曲线(b),其中将选择晶体管的阈值确定为1V。在编程状态下,将电子注入浮置栅极,这样,浮置栅极晶体管量的阈值电压约等于7V,并且存储器单元的特性给定为如同曲线(c)。
然而,这种传统的闪存单元在一个存储单元中只能存储1位信息。如果可形成在一个存储单元中能存储至少2位信息的闪存单元,就可以将传统闪存单元的存储器集成密度至少提高两倍。
发明内容
本发明的目的是为了解决在现有技术中出现的问题,因此,本发明的一个目的是提供一种能够在一个存储单元结构中存储至少2位信息的多位闪存单元及其制造方法。本发明的另一个目的是提供一种以与传统隧道氧化物层相同的面积形成双隧道氧化物层的多位闪存单元,该闪存单元以至少两种编程和擦写电压进行驱动。
根据本发明的一个方案,提供一种闪存单元,包括:隧道氧化物层,其包括在半导体衬底上具有第一厚度的第一隧道和具有第二厚度的第二隧道;电荷存储层,形成在隧道氧化物层上;绝缘层,形成在电荷存储层上;以及控制栅极,形成在绝缘层上,并供以驱动电源。在此,第一隧道的第一厚度可比第二隧道的第二厚度薄。
根据本发明的另一个方案,提供一种制造闪存单元的方法,该方法包括步骤:在半导体衬底的有源器件区上形成第一隧道氧化物层,其中所述有源器件区由至少两个隔离层所限定;通过光刻以及蚀刻工艺去除部分所述第一隧道氧化物层;在所述半导体衬底的所述有源器件区上形成第二隧道氧化物层;在所述第一隧道氧化物层和第二隧道氧化物层上形成电荷存储层;在所述电荷存储层上形成绝缘层;以及在所述绝缘层上形成控制栅极。
附图说明
图1为传统堆叠栅极型闪存单元的剖视图;
图2为示出传统堆叠栅极型闪存单元的电压-电流特性的曲线图;
图3为根据本发明包括双隧道氧化物层的闪存单元的剖视图;
图4A和图4B为说明根据本发明的闪存单元制造方法的剖视图;以及
图5为示出根据本发明闪存单元的电压-电流特性的曲线图。
具体实施方式
以下,将参照附图详细描述根据本发明的包括双隧道氧化物层的闪存单元及其制造方法。
实施例1
图3为根据本发明包括双隧道氧化物层的闪存单元的剖视图。如图3所示,闪存单元包括双隧道氧化物层,其中在半导体衬底10上形成具有第一厚度的第一隧道20a和具有第二厚度的第二隧道20b。在此,第一隧道20a的第一厚度比第二隧道20b的第二厚度要薄。
进而,在第一隧道20a和第二隧道20b上形成电荷存储层22。当电荷存储层22由多晶硅形成时,闪存单元形成堆叠栅极型闪存单元,其具有两重栅极结构,包括浮置栅极和控制栅极。或者,电荷存储层22也可由氮化硅形成。在这种情况下,闪存单元包括硅-氧化物-氮化物-氧化物-硅(SONOS)介电层以及隧道氧化物层和绝缘层24。具有SONOS结构的闪存单元可使得栅极的高度降低,从而更加有利于提高集成度,并大幅降低运行电压。为了保证闪存单元更稳定地运行,优选地,电荷存储层22以基本上相同的面积覆盖隧道氧化物层的第一隧道20a和第二隧道20b。
在电荷存储层22上形成用于与控制栅极26绝缘的绝缘层24。在绝缘层24上形成控制栅极26,其中,驱动闪存单元的驱动电压施加在控制栅极26上。
图3所示的闪存单元包括由第一隧道20a和第二隧道20b构成的双隧道氧化物层,在一个单元结构中,第一隧道20a和第二隧道20b具有不同的厚度,因此在一个单元结构中可以存储2位信息。图5示出如图3所示2位闪存单元的电压VG-电流Id特性。如图5所示,在通过第一隧道20a的闪存单元的擦写和编程状态下,基于初始电压Vth1,存储器单元的特性分别给定为如曲线(a1)和(c1)。在此,曲线(b1)示出在初始状态下闪存单元的特性。与此不同,在通过第二隧道20b(厚度大于第一隧道20a)的闪存单元的擦写和编程状态下,基于初始电压Vth2,存储器单元的特性分别给定为如曲线(a2)和(c2)。在此,曲线(b2)示出第二隧道20b处,在初始状态下闪存单元的特性。
在这种方式下,图3所示2位闪存单元表现出在第一隧道20a和第二隧道20b处,编程和擦写状态分别互不相同的电压-电流特性。因此,发现在每个单元中,可以以2位来运行存储数据的功能。
实施例2
以下,参照图4A和4B描述根据本发明的包括双隧道氧化物层的闪存单元的制造方法。
首先,在衬底10中形成限定有源器件区的隔离层12,例如浅沟槽隔离(STI)层。通过热氧化处理将限定的有源器件区中的衬底表面进行氧化,然后在衬底的氧化表面上形成光致抗蚀剂图案30。之后,利用光致抗蚀剂图案30作为掩模蚀刻通过对衬底的氧化处理形成的部分氧化物层。此时,优选地,利用湿法蚀刻来去除该氧化物层,以防止损伤衬底。在去除该部分氧化物层后,在图4A中用附图标记21a表示剩余的氧化物层。
接着,在剥离光致抗蚀剂图案30后,衬底的有源器件区再次经过热氧化处理,从而形成图4B中的氧化物层21b。在这种方式下,当进行两步氧化物层形成过程时,通过形成氧化物层的第一过程去除的一部分氧化物层的左手部分仅具有第二氧化物层21b,而右手部分具有第一氧化物层21a和第二氧化物层21b,其中第一氧化物层21a和第二氧化物层21b互相重叠,重叠的厚度大于其中任何一个氧化物层的厚度。换而言之,与右侧形成的氧化物层相比,左侧形成的氧化物层的厚度相对更薄。
接着,当利用形成闪存栅极的常规方法形成电荷存储层22、绝缘层24以及控制栅极26时,就可形成如图3中包括双隧道氧化物层的闪存的存储单元。
如同上述,根据本发明,可以形成在一个单元中能够存储至少2位信息的多位闪存单元结构。与传统闪存单元相比,可以形成在给定的存储区域中将存储器集成密度至少提高两倍的闪存,因此可以大幅提高半导体的芯片集成密度。此外,在形成存储单元阵列的过程中,对具有双隧道氧化物层的单位单元进行不同处理,可以形成实现更高功能的存储单元阵列。
尽管参照优选实施例示出和描述了本发明,所属领域技术人员应当理解,在不脱离如所附权利要求限定的本发明的精神和范围的条件下,可进行各种变化和修改。
Claims (10)
1.一种闪存单元,包括:
隧道氧化物层,其包括在半导体衬底上具有第一厚度的第一隧道和具有第二厚度的第二隧道;
电荷存储层,形成在所述隧道氧化物层上;
绝缘层,形成在所述电荷存储层上;以及
控制栅极,形成在所述绝缘层上,并以驱动电源对其供电。
2.如权利要求1所述的闪存单元,其中,所述第一隧道的第一厚度比所述第二隧道的第二厚度薄。
3.如权利要求1所述的闪存单元,其中,所述电荷存储层以基本上相同的面积覆盖所述隧道氧化物层的所述第一隧道和所述第二隧道。
4.如权利要求1所述的闪存单元,其中,所述电荷存储层由多晶硅形成,并且具有两重栅极结构以及所述控制栅极。
5.如权利要求1所述的闪存单元,其中,所述电荷存储层由氮化硅形成,并且具有硅-氧化物-氮化物-氧化物-硅介电层以及隧道氧化物层和绝缘层。
6.一种闪存单元的制造方法,该方法包括以下步骤:
在半导体衬底的有源器件区上形成第一隧道氧化物层,其中所述有源器件区由至少两个隔离层所限定;
通过光刻以及蚀刻工艺去除部分所述第一隧道氧化物层;
在所述半导体衬底的所述有源器件区上形成第二隧道氧化物层;
在所述第一隧道氧化物层和所述第二隧道氧化物层上形成电荷存储层;
在所述电荷存储层上形成绝缘层;以及
在所述绝缘层上形成控制栅极。
7.如权利要求6所述的方法,其中,所述第一隧道氧化物层的厚度比所述第二隧道氧化物层的厚度薄。
8.如权利要求6所述的方法,其中,所述电荷存储层以基本上相同的面积覆盖所述第一隧道氧化物层和所述第二隧道氧化物层。
9.如权利要求6所述的方法,其中,所述电荷存储层由多晶硅形成。
10.如权利要求6所述的方法,其中,所述电荷存储层由氮化硅形成。
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KR1020050129758A KR100731058B1 (ko) | 2005-12-26 | 2005-12-26 | 이중 터널 산화막을 포함하는 플래시 메모리 셀 및 그 제조방법 |
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Cited By (3)
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CN103296080A (zh) * | 2012-02-22 | 2013-09-11 | 旺宏电子股份有限公司 | 半导体结构及其形成方法 |
CN105633151A (zh) * | 2014-11-04 | 2016-06-01 | 中国科学院微电子研究所 | 一种非对称FinFET结构及其制造方法 |
CN113764530A (zh) * | 2020-06-03 | 2021-12-07 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
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KR100871605B1 (ko) | 2007-08-30 | 2008-12-02 | 고려대학교 산학협력단 | 멀티 비트 프로그램이 가능한 비휘발성 메모리 소자 및이를 제조하는 방법 |
KR101055038B1 (ko) | 2009-12-21 | 2011-08-05 | 한양대학교 산학협력단 | 서로 다른 두께의 블로킹 유전막을 가지는 핀 펫 타입의 플래시 메모리 |
JP2012199313A (ja) * | 2011-03-18 | 2012-10-18 | Toshiba Corp | 不揮発性半導体記憶装置 |
CN105336740B (zh) | 2014-08-13 | 2019-11-19 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
TWI663711B (zh) * | 2016-12-23 | 2019-06-21 | 聯華電子股份有限公司 | 半導體元件及其製造方法 |
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-
2005
- 2005-12-26 KR KR1020050129758A patent/KR100731058B1/ko not_active IP Right Cessation
-
2006
- 2006-12-19 US US11/613,096 patent/US20070145472A1/en not_active Abandoned
- 2006-12-25 CN CNA2006101712615A patent/CN1992345A/zh active Pending
Cited By (5)
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CN103296080A (zh) * | 2012-02-22 | 2013-09-11 | 旺宏电子股份有限公司 | 半导体结构及其形成方法 |
CN103296080B (zh) * | 2012-02-22 | 2015-09-09 | 旺宏电子股份有限公司 | 半导体结构及其形成方法 |
CN105633151A (zh) * | 2014-11-04 | 2016-06-01 | 中国科学院微电子研究所 | 一种非对称FinFET结构及其制造方法 |
CN105633151B (zh) * | 2014-11-04 | 2019-03-26 | 中国科学院微电子研究所 | 一种非对称FinFET结构及其制造方法 |
CN113764530A (zh) * | 2020-06-03 | 2021-12-07 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
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US20070145472A1 (en) | 2007-06-28 |
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