CN105336740B - 半导体元件及其制作方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000002360 preparation method Methods 0.000 title abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 87
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- 230000015654 memory Effects 0.000 claims description 22
- 238000003475 lamination Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000005641 tunneling Effects 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 239000002689 soil Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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Abstract
本发明公开一种半导体元件及其制作方法,该半导体元件包含一基底、一浮置栅极设于基底上、一第一氧化硅层设于浮置栅极与基底之间、一第一穿隧氧化层与一第二穿隧氧化层分别设于第一氧化硅层两端以及一控制栅极设于浮置栅极上。其中第一穿隧氧化层及第二穿隧氧化层的厚度均低于第一氧化硅层的厚度。
Description
技术领域
本发明涉及一种闪存存储器元件,尤其是涉及一种于浮置栅极与基底之间形成两个穿隧氧化(tunnel oxide)层的闪存存储器元件及其制作方法。
背景技术
闪存存储器(flash memory)是一种非挥发性(non-volatile)存储器,其在缺乏外部电源供应时,亦能够保存存储在存储器中的资讯内容。近几年来,由于闪存存储器具有可重复写入以及可被电抹除等优点,因此,已被广泛地应用在移动电话(mobile phone)、数字相机(digital camera)、游戏机(video player)、个人数字助理(personal digitalassistant,PDA)等电子产品或正在发展中的系统单芯片(system on a chip,SOC)中。
然而,现今闪存存储器架构中通常仅利用单边的穿隧氧化层来进行写入或抹除等操作,而此操作方式不但影响整个存储器的运作速度,更容易降低存储器的耐久性(endurance)及寿命。因此如何改良现有架构与操作方式以提升闪存存储器的整体耐久性即为现今一重要课题。
发明内容
为解决上述问题,本发明提供一种半导体元件,包含一基底、一浮置栅极设于基底上、一第一氧化硅层设于浮置栅极与基底之间、一第一穿隧氧化层与一第二穿隧氧化层分别设于第一氧化硅层两端、一控制栅极设于浮置栅极上以及一选择栅极设于第一穿隧氧化层旁。其中第一穿隧氧化层及第二穿隧氧化层的厚度均低于第一氧化硅层的厚度。
本发明另一实施例是公开一种操作存储器单元的方法,其中该存储器单元具有一浮置栅极于一基底上、一图案化的ONO堆叠层于该浮置栅极上、一控制栅极于该ONO堆叠层上、一第一穿隧氧化层与一第二穿隧氧化层设于该浮置栅极及该基底之间、一选择栅极设于该第一穿隧氧化层旁、一漏极区域于该选择栅极旁以及一源极区域于该第二穿隧氧化层旁。该方法包含于写入操作(program operation)时先对漏极区域施加一第一电压、对选择栅极施加一第二电压,且该第二电压高于该第一电压以及施加0伏电压至控制栅极并使电子存入浮置栅极中。该方法另包含于抹除操作(erase operation)时于漏极区域呈浮置状态时施加0伏电压至选择栅极,然后施加一第三电压至控制栅极并使电子从第二穿隧氧化层中释放出来。
本发明另一实施例是公开一种制作半导体元件的方法。首先提供一基底,然后形成一介电堆叠层于基底上,其中该介电堆叠层包含一第一氧化硅层与一第一氮化硅层。接着图案化介电堆叠层、去除部分第一氧化硅层以于第一氮化硅层两端下方形成二开口、形成多个第二氧化硅层于该等二开口内、形成一间隙壁于该等第二氧化硅层上以及形成多个第三氧化硅层于该等第二氧化硅层旁。
附图说明
图1至图7为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 介电堆叠层
16 氧化硅层 18 氮化硅层
20 图案化光致抗蚀剂 22 开口
24 氧化硅层 26 N+区域
28 间隙壁 30 氧化硅层
32 第一穿隧氧化层 34 第二穿隧氧化层
36 浮置栅极 38 ONO堆叠层
40 控制栅极 42 选择栅极
44 漏极区域 46 源极区域
48 栅极氧化层 50 间隙壁
具体实施方式
请参照图1至图7,图1至图7为本发明优选实施例制作一半导体元件的方法示意图。如图1所示,首先提供一基底12,例如一由硅、砷化镓、硅覆绝缘(SOI)层、外延层、硅锗层或其他半导体基底材料所构成的基底,然后形成一介电堆叠层14于基底12上。在本实施例中,介电堆叠层14优选包含一氧化硅层16与一氮化硅层18设于氧化硅层16上,且氮化硅层18上又可选择性再设置一四乙氧基硅烷(Tetraethylorthosilicate,TEOS)层(图未示)。
接着形成一图案化光致抗蚀剂20于介电堆叠层14上,然后利用蚀刻制作工艺于氮化硅层18底部形成底切(undercut),例如图2所示,利用图案化光致抗蚀剂20为掩模进行一蚀刻制作工艺去除部分氮化硅层18但不去除任何氧化硅层16。随后进行一干蚀刻制作工艺去除未被氮化硅层18所覆盖的氧化硅层16,使氧化硅层16边缘略与氮化硅层18边缘切齐后再进行一湿蚀刻制作工艺去除部分位于氮化硅层18下方的氧化硅层16,以于氮化硅层18两端的正下方形成二开口22。之后再去除图案化光致抗蚀剂20。
如图3所示,然后进行一氧化制作工艺以形成多个氧化硅层24于二开口22内,并进行一N型离子注入以于基底12中形成一埋入N+区域26。需注意的是,所形成的氧化硅层24厚度优选低于之前氧化硅层16的厚度。
接着如图4所示,再形成一氮化硅层(图未示)于基底12、氧化硅层24及氮化硅层18上,并去除部分该氮化硅层以于氧化硅层24上形成一间隙壁28。在本实施例中,由于部分氮化硅层深入之前所形成的两个开口22内,因此所形成的间隙壁28由左右两边观察时优选包含一正L型与一倒L型。
随后如图5所示,再进行另一氧化制作工艺以形成多个氧化硅层30于氧化硅层24旁,其中氧化硅层30的厚度优选高于氧化硅层24的厚度。
接着如图6所示,先去除该氮化硅层18及间隙壁28并裸露出下面的氧化硅层16、24、30,去除氧化硅层24,然后再进行一氧化制作工艺形成一第一穿隧氧化层32与一第二穿隧氧化层34于氧化硅层30及氧化硅层16之间。由于氧化硅层24于前述形成N+区域26时多少被注入基底12的离子污染,因此本实施例优选以另一道氧化制作工艺形成新的氧化硅层作为穿隧氧化层来确保后续存储器元件进行程序操作时电子移动的品质。
之后先全面性依序形成一第一栅极层(图未示)于第一穿隧氧化层32、第二穿隧氧化层34、氧化硅层30及氧化硅层16上、一氧化硅-氮化硅-氧化硅(oxide-nitride-oxide,ONO)堆叠层(图未示)于该第一栅极层上以及一第二栅极层(图未示)于ONO堆叠层上。然后图案化该第二栅极层、该ONO堆叠层以及该第一栅极层,以形成一浮置栅极36于第一穿隧氧化层32、第二穿隧氧化层34、氧化硅层30及氧化硅层16上、一图案化的ONO堆叠层38于浮置栅极36上以及一控制栅极40于ONO堆叠层38上。
然后如图7所示,形成一栅极氧化层48与一第三栅极层(图未示)于基底12上,图案化该第三栅极层与栅极氧化层48以形成一选择栅极42于第一穿隧氧化层32旁。于各栅极结构周围形成间隙壁50,再形成一漏极区域44于选择栅极42旁以及一源极区域46于第二穿隧氧化层34旁。至此即完成本发明优选实施例的一闪存存储器元件的制作。
如图7所示,本发明又公开一种半导体元件结构,其包含一基底12、一浮置栅极36设于基底12上、一氧化硅层16与多个氧化硅层30设于浮置栅极.36与基底12之间、一第一穿隧氧化层32与第二穿隧氧化层34分别设于氧化硅层16与氧化硅层30之间、一控制栅极40设于浮置栅极36上、一ONO堆叠层38设于浮置栅极36与控制栅极40之间、一选择栅极42设于第一穿隧氧化层32旁、一漏极区域44设于选择栅极42旁以及一源极区域46于第二穿隧氧化层34旁。其中第一穿隧氧化层32及第二穿隧氧化层34的厚度优选低于该氧化硅层16与氧化硅层30的厚度。
另依据前述的存储器单元结构,本发明另一实施例公开一种操作存储器单元的方法,其主要利用结构中的两个穿隧氧化层32、34于进行写入、抹除等操作时来提升整个元件的耐久性(endurance),进而提升元件的效能与寿命。举例来说,本发明可于进行写入操作(program operation)时先对漏极区域44施加一第一电压,例如13伏电压,然后对选择栅极42施加一高于该第一电压的第二电压,例如15伏电压,之后再施加0伏电压至控制栅极40并使电子从第一穿隧氧化层32存入浮置栅极36中,以完成写入的动作。另外于进行抹除操作(erase operation)时,可于漏极区域44呈浮置状态时施加0伏电压至选择栅极42,之后施加一第三电压,例如13伏电压至控制栅极40并使电子从第二穿隧氧化层34中释放出来,以完成抹除的动作。
综上所述,相比较于现有闪存存储器架构仅利用单边的穿隧氧化层来进行写入或抹除等操作,本发明主要于浮置栅极与基底之间形成左右设置的两个穿隧氧化层,并利用这两个穿隧氧化层来进行写入与抹除等操作。如此不但可提升整个存储器的运作速度,更可延长存储器的耐久性(endurance)及寿命。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (13)
1.一种半导体元件,包含:
基底;
浮置栅极,设于该基底上;
第一氧化硅层,设于该浮置栅极与该基底之间;
第一穿隧氧化层与第二穿隧氧化层,分别设于该第一氧化硅层两端,其中该第一穿隧氧化层及该第二穿隧氧化层的厚度低于该第一氧化硅层的厚度;
控制栅极,设于该浮置栅极上;以及
多个第三氧化硅层,设于该第一穿隧氧化层与该第二穿隧氧化层旁,且该多个第三氧化硅层的侧壁与该浮置栅极的侧壁切齐。
2.如权利要求1所述的半导体元件,还包含一氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆叠层,设于该浮置栅极与该控制栅极之间。
3.如权利要求1所述的半导体元件,其中该多个第三氧化硅层的厚度高于该第一穿隧氧化层与该第二穿隧氧化层的厚度。
4.一种操作存储器单元的方法,该存储器单元具有浮置栅极于一基底上、图案化的ONO堆叠层于该浮置栅极上、控制栅极于该ONO堆叠层上、第一穿隧氧化层、第二穿隧氧化层、第一氧化硅层以及多个第三氧化硅层设于该浮置栅极及该基底之间,其中该第一氧化硅层位于该第一穿隧氧化层与该第二穿隧氧化层之间,该第一穿隧氧化层位于该第一氧化硅层与一该第三氧化硅层之间,该第二穿隧氧化层位于该第一氧化硅层与另一该第三氧化硅层之间,该浮置栅极的侧壁与该多个第三氧化硅层的侧壁切齐、选择栅极设于该第一穿隧氧化层旁、漏极区域于该选择栅极旁以及源极区域于该第二穿隧氧化层旁,该方法包含:
在写入操作(program operation)时包含:
对该漏极区域施加一第一电压;
对该选择栅极施加一第二电压,其中该第二电压高于该第一电压;以及
施加0伏电压至该控制栅极并使电子从该第一穿隧氧化层存入该浮置栅极中;
在抹除操作(erase operation)时包含:
在该漏极区域呈浮置状态时施加0伏电压至该选择栅极;以及
施加一第三电压至该控制栅极并使电子从该第二穿隧氧化层中释放出来。
5.一种制作半导体元件的方法,包含:
提供一基底;
形成一介电堆叠层于该基底上,其中该介电堆叠层包含第一氧化硅层与第一氮化硅层;
图案化该介电堆叠层;
去除部分该第一氧化硅层以于该第一氮化硅层两端下方形成二开口;
形成多个第二氧化硅层于该等二开口内;
形成一间隙壁于该多个第二氧化硅层上;
形成多个第三氧化硅层于该多个第二氧化硅层旁;
在形成该多个第三氧化硅层后去除该第一氮化硅层及该间隙壁;
去除该多个第二氧化硅层;以及
形成一第一穿隧氧化层与一第二穿隧氧化层于该多个第三氧化硅层及该第一氧化层之间;
形成一浮置栅极于该第一穿隧氧化层、该第二穿隧氧化层、该多个第三氧化硅层及该第一氧化硅层上,其中该浮置栅极的侧壁对齐于该多个第三氧化硅层的侧壁。
6.如权利要求5所述的方法,还包含:
形成一图案化光致抗蚀剂于该介电堆叠层上;
利用该图案化光致抗蚀剂为掩模图案化该介电堆叠层以去除部分该第一氮化硅层;
进行一干蚀刻制作工艺以去除不被该第一氮化硅层所覆盖的第一氧化硅层;
进行一湿蚀刻制作工艺以去除部分位于该第一氮化硅层下方的第一氧化硅层以于该第一氮化硅层两端下方形成二开口;以及
去除该图案化光致抗蚀剂。
7.如权利要求5所述的方法,还包含于形成该多个第二氧化硅层后进行一N型离子注入以于该基底中形成一埋入N+区域。
8.如权利要求5所述的方法,其中,形成该间隙壁的方法包含:
形成一第二氮化硅层于该基底、该多个第二氧化硅层及该第一氮化硅层上;以及
去除部分该第二氮化硅层以于该多个第二氧化硅层上形成该间隙壁。
9.如权利要求8所述的方法,其中该间隙壁包含一正L型以及一倒L型。
10.如权利要求5所述的方法,其中该多个第三氧化硅层的厚度大于该多个第二氧化硅层的厚度。
11.如权利要求5所述的方法,其中该多个第三氧化硅层的厚度大于该第一穿隧氧化层与该第二穿隧氧化层的厚度。
12.如权利要求5所述的方法,其中该第一氧化硅层的厚度大于该第一穿隧氧化层与该第二穿隧氧化层的厚度。
13.如权利要求5所述的方法,还包含;
形成一图案化的氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)堆叠层于该浮置栅极上以及形成一控制栅极于该ONO堆叠层上;
形成一选择栅极于该第一穿隧氧化层旁;以及
形成一漏极区域于该选择栅极旁以及一源极区域于该多个第三氧化硅层旁。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5960285A (en) * | 1997-06-24 | 1999-09-28 | United Semiconductor Corp. | Flash EEPROM device |
CN1694243A (zh) * | 2004-04-30 | 2005-11-09 | 三星电子株式会社 | 电可擦编程只读存储器单元的制造方法 |
CN1716615A (zh) * | 2004-06-09 | 2006-01-04 | 东部亚南半导体株式会社 | 非易失性存储器件及其驱动方法 |
CN101388339A (zh) * | 2007-04-09 | 2009-03-18 | 台湾积体电路制造股份有限公司 | 半导体元件以及制作半导体元件的方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5273923A (en) * | 1991-10-09 | 1993-12-28 | Motorola, Inc. | Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions |
US5714412A (en) | 1996-12-02 | 1998-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-level, split-gate, flash memory cell and method of manufacture thereof |
JP3502531B2 (ja) * | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US5972752A (en) * | 1997-12-29 | 1999-10-26 | United Semiconductor Corp. | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile |
KR100579844B1 (ko) * | 2003-11-05 | 2006-05-12 | 동부일렉트로닉스 주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
KR100618843B1 (ko) * | 2004-07-12 | 2006-09-01 | 삼성전자주식회사 | 비휘발성 반도체 메모리 소자 및 그 제조방법 |
KR100676204B1 (ko) * | 2005-08-25 | 2007-01-30 | 삼성전자주식회사 | 이이피롬 셀 트랜지스터 |
KR100731058B1 (ko) * | 2005-12-26 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 이중 터널 산화막을 포함하는 플래시 메모리 셀 및 그 제조방법 |
US20080061359A1 (en) * | 2006-02-04 | 2008-03-13 | Chungho Lee | Dual charge storage node with undercut gate oxide for deep sub-micron memory cell |
US7432156B1 (en) * | 2006-04-20 | 2008-10-07 | Spansion Llc | Memory device and methods for its fabrication |
TW200808056A (en) * | 2006-07-26 | 2008-02-01 | Compal Communications Inc | Rear projection display system |
US8012830B2 (en) * | 2007-08-08 | 2011-09-06 | Spansion Llc | ORO and ORPRO with bit line trench to suppress transport program disturb |
FR2996680A1 (fr) * | 2012-10-10 | 2014-04-11 | St Microelectronics Rousset | Memoire non volatile comportant des transistors de selection verticaux |
-
2014
- 2014-08-13 CN CN201410395988.6A patent/CN105336740B/zh active Active
- 2014-09-17 US US14/489,439 patent/US9490016B2/en active Active
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2016
- 2016-09-28 US US15/279,410 patent/US10243084B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5960285A (en) * | 1997-06-24 | 1999-09-28 | United Semiconductor Corp. | Flash EEPROM device |
CN1694243A (zh) * | 2004-04-30 | 2005-11-09 | 三星电子株式会社 | 电可擦编程只读存储器单元的制造方法 |
CN1716615A (zh) * | 2004-06-09 | 2006-01-04 | 东部亚南半导体株式会社 | 非易失性存储器件及其驱动方法 |
CN101388339A (zh) * | 2007-04-09 | 2009-03-18 | 台湾积体电路制造股份有限公司 | 半导体元件以及制作半导体元件的方法 |
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