CN1988143A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1988143A CN1988143A CNA2006100738675A CN200610073867A CN1988143A CN 1988143 A CN1988143 A CN 1988143A CN A2006100738675 A CNA2006100738675 A CN A2006100738675A CN 200610073867 A CN200610073867 A CN 200610073867A CN 1988143 A CN1988143 A CN 1988143A
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- organic insulating
- insulating film
- semiconductor device
- electrode
- layer
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
Claims (15)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-367210 | 2005-12-20 | ||
JP2005367210 | 2005-12-20 | ||
JP2005367210A JP5118300B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1988143A true CN1988143A (zh) | 2007-06-27 |
CN1988143B CN1988143B (zh) | 2011-07-27 |
Family
ID=38172508
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006100738675A Expired - Fee Related CN1988143B (zh) | 2005-12-20 | 2006-04-06 | 半导体器件及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7417326B2 (zh) |
JP (1) | JP5118300B2 (zh) |
KR (1) | KR100786163B1 (zh) |
CN (1) | CN1988143B (zh) |
TW (1) | TWI305021B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104091793B (zh) * | 2014-07-18 | 2016-09-21 | 华进半导体封装先导技术研发中心有限公司 | 提高可靠性的微凸点结构及制作方法 |
CN108962869A (zh) * | 2017-05-23 | 2018-12-07 | 矽品精密工业股份有限公司 | 基板结构及其制法 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100772920B1 (ko) * | 2006-02-20 | 2007-11-02 | 주식회사 네패스 | 솔더 범프가 형성된 반도체 칩 및 제조 방법 |
JP2008078382A (ja) * | 2006-09-21 | 2008-04-03 | Toshiba Corp | 半導体装置とその製造方法 |
US8446008B2 (en) * | 2006-12-25 | 2013-05-21 | Rohm Co., Ltd. | Semiconductor device bonding with stress relief connection pads |
US8436467B2 (en) * | 2007-06-15 | 2013-05-07 | Rohm Co., Ltd. | Semiconductor device |
US8132321B2 (en) * | 2008-08-13 | 2012-03-13 | Unimicron Technology Corp. | Method for making embedded circuit structure |
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2005
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2006
- 2006-03-14 US US11/374,134 patent/US7417326B2/en active Active
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- 2006-04-05 KR KR1020060030781A patent/KR100786163B1/ko active IP Right Grant
- 2006-04-06 CN CN2006100738675A patent/CN1988143B/zh not_active Expired - Fee Related
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CN104091793B (zh) * | 2014-07-18 | 2016-09-21 | 华进半导体封装先导技术研发中心有限公司 | 提高可靠性的微凸点结构及制作方法 |
CN108962869A (zh) * | 2017-05-23 | 2018-12-07 | 矽品精密工业股份有限公司 | 基板结构及其制法 |
CN108962869B (zh) * | 2017-05-23 | 2022-07-05 | 矽品精密工业股份有限公司 | 基板结构及其制法 |
Also Published As
Publication number | Publication date |
---|---|
KR20070065765A (ko) | 2007-06-25 |
CN1988143B (zh) | 2011-07-27 |
US7417326B2 (en) | 2008-08-26 |
US20080293234A1 (en) | 2008-11-27 |
TWI305021B (en) | 2009-01-01 |
TW200725765A (en) | 2007-07-01 |
KR100786163B1 (ko) | 2007-12-21 |
US8420522B2 (en) | 2013-04-16 |
JP2007173415A (ja) | 2007-07-05 |
JP5118300B2 (ja) | 2013-01-16 |
US20070138635A1 (en) | 2007-06-21 |
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