CN1914722B - 制作应变绝缘体上硅结构的方法及用此方法形成的绝缘体上硅结构 - Google Patents
制作应变绝缘体上硅结构的方法及用此方法形成的绝缘体上硅结构 Download PDFInfo
- Publication number
- CN1914722B CN1914722B CN2005800031333A CN200580003133A CN1914722B CN 1914722 B CN1914722 B CN 1914722B CN 2005800031333 A CN2005800031333 A CN 2005800031333A CN 200580003133 A CN200580003133 A CN 200580003133A CN 1914722 B CN1914722 B CN 1914722B
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- active layer
- region
- insulating layer
- layer
- strained
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- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6744—Monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Silicon Compounds (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/814,482 | 2004-03-31 | ||
| US10/814,482 US8450806B2 (en) | 2004-03-31 | 2004-03-31 | Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby |
| PCT/EP2005/051319 WO2005096372A1 (en) | 2004-03-31 | 2005-03-22 | Method for fabricating strained silicon-on-insulator structures and strained silicon-on -insulator structures formed thereby |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1914722A CN1914722A (zh) | 2007-02-14 |
| CN1914722B true CN1914722B (zh) | 2013-01-23 |
Family
ID=34961842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005800031333A Expired - Fee Related CN1914722B (zh) | 2004-03-31 | 2005-03-22 | 制作应变绝缘体上硅结构的方法及用此方法形成的绝缘体上硅结构 |
Country Status (13)
| Country | Link |
|---|---|
| US (2) | US8450806B2 (enExample) |
| EP (1) | EP1738410B1 (enExample) |
| JP (1) | JP5039901B2 (enExample) |
| KR (1) | KR100961809B1 (enExample) |
| CN (1) | CN1914722B (enExample) |
| AT (1) | ATE398834T1 (enExample) |
| CA (1) | CA2559219C (enExample) |
| DE (1) | DE602005007592D1 (enExample) |
| IL (1) | IL178387A (enExample) |
| IN (1) | IN2015DN00261A (enExample) |
| MX (1) | MXPA06007643A (enExample) |
| TW (1) | TWI404145B (enExample) |
| WO (1) | WO2005096372A1 (enExample) |
Families Citing this family (51)
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| US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
| US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
| US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
| US7105390B2 (en) | 2003-12-30 | 2006-09-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
| US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
| US8450806B2 (en) | 2004-03-31 | 2013-05-28 | International Business Machines Corporation | Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby |
| JP4878738B2 (ja) * | 2004-04-30 | 2012-02-15 | 株式会社ディスコ | 半導体デバイスの加工方法 |
| US7579280B2 (en) | 2004-06-01 | 2009-08-25 | Intel Corporation | Method of patterning a film |
| US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
| US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
| JP5113999B2 (ja) * | 2004-09-28 | 2013-01-09 | シャープ株式会社 | 水素イオン注入剥離方法 |
| US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
| US7332439B2 (en) | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
| US7361958B2 (en) | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
| US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
| US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
| US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
| US20060202266A1 (en) | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
| US20060226492A1 (en) * | 2005-03-30 | 2006-10-12 | Bich-Yen Nguyen | Semiconductor device featuring an arched structure strained semiconductor layer |
| US7439165B2 (en) * | 2005-04-06 | 2008-10-21 | Agency For Sceince, Technology And Reasearch | Method of fabricating tensile strained layers and compressive strain layers for a CMOS device |
| US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
| US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
| US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
| US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
| US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
| US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
| US7575975B2 (en) * | 2005-10-31 | 2009-08-18 | Freescale Semiconductor, Inc. | Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer |
| US7615806B2 (en) * | 2005-10-31 | 2009-11-10 | Freescale Semiconductor, Inc. | Method for forming a semiconductor structure and structure thereof |
| US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
| US7396711B2 (en) | 2005-12-27 | 2008-07-08 | Intel Corporation | Method of fabricating a multi-cornered film |
| US20070224838A1 (en) * | 2006-03-27 | 2007-09-27 | Honeywell International Inc. | Method of straining a silicon island for mobility improvement |
| US7449373B2 (en) | 2006-03-31 | 2008-11-11 | Intel Corporation | Method of ion implanting for tri-gate devices |
| US20070257310A1 (en) * | 2006-05-02 | 2007-11-08 | Honeywell International Inc. | Body-tied MOSFET device with strained active area |
| US9305859B2 (en) * | 2006-05-02 | 2016-04-05 | Advanced Analogic Technologies Incorporated | Integrated circuit die with low thermal resistance |
| US7585711B2 (en) * | 2006-08-02 | 2009-09-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor-on-insulator (SOI) strained active area transistor |
| US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
| US7538391B2 (en) * | 2007-01-09 | 2009-05-26 | International Business Machines Corporation | Curved FINFETs |
| US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
| RU2382437C1 (ru) * | 2008-08-18 | 2010-02-20 | Институт физики полупроводников Сибирского отделения Российской академии наук | Способ изготовления структуры кремний-на-изоляторе |
| US8558279B2 (en) | 2010-09-23 | 2013-10-15 | Intel Corporation | Non-planar device having uniaxially strained semiconductor body and method of making same |
| CN103377930B (zh) * | 2012-04-19 | 2015-11-25 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
| US8859348B2 (en) * | 2012-07-09 | 2014-10-14 | International Business Machines Corporation | Strained silicon and strained silicon germanium on insulator |
| CN103811349A (zh) * | 2012-11-06 | 2014-05-21 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
| US9306066B2 (en) | 2014-02-28 | 2016-04-05 | Qualcomm Incorporated | Method and apparatus of stressed FIN NMOS FinFET |
| US9391198B2 (en) | 2014-09-11 | 2016-07-12 | Globalfoundries Inc. | Strained semiconductor trampoline |
| KR102251061B1 (ko) | 2015-05-04 | 2021-05-14 | 삼성전자주식회사 | 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법 |
| US9373624B1 (en) | 2015-06-11 | 2016-06-21 | International Business Machines Corporation | FinFET devices including epitaxially grown device isolation regions, and a method of manufacturing same |
| US9608068B2 (en) | 2015-08-05 | 2017-03-28 | International Business Machines Corporation | Substrate with strained and relaxed silicon regions |
| US20190081145A1 (en) * | 2017-09-12 | 2019-03-14 | Globalfoundries Inc. | Contact to source/drain regions and method of forming same |
| US10468486B2 (en) | 2017-10-30 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company Ltd. | SOI substrate, semiconductor device and method for manufacturing the same |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6630699B1 (en) * | 2000-08-31 | 2003-10-07 | Lucent Technologies, Inc. | Transistor device having an isolation structure located under a source region, drain region and channel region and a method of manufacture thereof |
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-
2004
- 2004-03-31 US US10/814,482 patent/US8450806B2/en active Active
-
2005
- 2005-03-22 DE DE602005007592T patent/DE602005007592D1/de not_active Expired - Lifetime
- 2005-03-22 IN IN261DEN2015 patent/IN2015DN00261A/en unknown
- 2005-03-22 JP JP2007505543A patent/JP5039901B2/ja not_active Expired - Fee Related
- 2005-03-22 CN CN2005800031333A patent/CN1914722B/zh not_active Expired - Fee Related
- 2005-03-22 MX MXPA06007643A patent/MXPA06007643A/es active IP Right Grant
- 2005-03-22 EP EP05717124A patent/EP1738410B1/en not_active Expired - Lifetime
- 2005-03-22 CA CA2559219A patent/CA2559219C/en not_active Expired - Fee Related
- 2005-03-22 WO PCT/EP2005/051319 patent/WO2005096372A1/en not_active Ceased
- 2005-03-22 KR KR1020067015900A patent/KR100961809B1/ko not_active Expired - Fee Related
- 2005-03-22 TW TW094108847A patent/TWI404145B/zh not_active IP Right Cessation
- 2005-03-22 AT AT05717124T patent/ATE398834T1/de not_active IP Right Cessation
-
2006
- 2006-09-28 IL IL178387A patent/IL178387A/en not_active IP Right Cessation
-
2007
- 2007-10-29 US US11/926,613 patent/US7704855B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6630699B1 (en) * | 2000-08-31 | 2003-10-07 | Lucent Technologies, Inc. | Transistor device having an isolation structure located under a source region, drain region and channel region and a method of manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100961809B1 (ko) | 2010-06-08 |
| US20050227498A1 (en) | 2005-10-13 |
| US20080050931A1 (en) | 2008-02-28 |
| TWI404145B (zh) | 2013-08-01 |
| TW200532803A (en) | 2005-10-01 |
| JP2007531294A (ja) | 2007-11-01 |
| US7704855B2 (en) | 2010-04-27 |
| CA2559219C (en) | 2010-11-02 |
| ATE398834T1 (de) | 2008-07-15 |
| EP1738410B1 (en) | 2008-06-18 |
| EP1738410A1 (en) | 2007-01-03 |
| US8450806B2 (en) | 2013-05-28 |
| WO2005096372A1 (en) | 2005-10-13 |
| CA2559219A1 (en) | 2005-10-13 |
| CN1914722A (zh) | 2007-02-14 |
| KR20060126550A (ko) | 2006-12-07 |
| IL178387A (en) | 2010-12-30 |
| JP5039901B2 (ja) | 2012-10-03 |
| MXPA06007643A (es) | 2006-09-04 |
| IL178387A0 (en) | 2007-02-11 |
| DE602005007592D1 (de) | 2008-07-31 |
| IN2015DN00261A (enExample) | 2015-07-10 |
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