CN1665030A - 3d rram - Google Patents

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CN1665030A
CN1665030A CN2004100104312A CN200410010431A CN1665030A CN 1665030 A CN1665030 A CN 1665030A CN 2004100104312 A CN2004100104312 A CN 2004100104312A CN 200410010431 A CN200410010431 A CN 200410010431A CN 1665030 A CN1665030 A CN 1665030A
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许胜籐
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Eicke Fout Intellectual Property Co
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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Abstract

在硅基底上与外围电路一起形成在3D RRAM中使用的存储器阵列层；沉积和形成氧化硅、底部电极材料、氧化硅、电阻器材料、氧化硅、氮化硅、氧化硅、顶部电极以及覆盖氧化物的层。多个存储器阵列层彼此层叠形成。本发明的RRAM可以在单步或两步编程过程中编程。

Description

3D RRAM
技术领域
本发明涉及用于非易失存储器阵列应用的薄膜电阻存储器件，尤其涉及一种无需有源器件的电阻存储器件。
背景技术
现有技术的电阻存储器件阵列需要在非易失存储元件上的有源器件。然而，在电阻存储器件的情况下，这些器件是一个电阻器、一个晶体管的阵列，或一个电阻器、一个二极管的阵列，这些阵列不适合在超高密度存储器集成的三维阵列中使用。在此公开的发明解决上述问题，因为该发明的存储器单元可以结合到大的存储器阵列中，并且无需有源器件。
发明内容
3D RRAM中使用的存储器阵列层在其上具有外围电路的硅基底上形成，该存储器阵列层包括沉积和平面化的第一氧化硅层；底部电极，由选自Pt、PtRhOx、PtIrOx以及TiN/Pt构成的材料组的材料形成；沉积的第二氧化物层，其厚度至少为底部电极厚度的1.5倍，其被平面化以达到暴露底部电极的水平；存储电阻器材料层；Si3N4层；第三氧化物层，其厚度大约为存储电阻器材料的厚度的1.5倍；进行CMP以暴露存储电阻器表面；顶部电极，由选自Pt、PtRhOxPtIrOx以及TiN/Pt构成的材料组的材料制成；覆盖氧化物层。多个存储器阵列层彼此层叠形成。
单步编程3D RRAM的方法包括：选择要写入的存储单元；将高电压编程脉冲施加到第一相关位线；将低电压编程脉冲施加到第二相关位线；浮动关联的字线；用半编程脉冲电压来偏置所有其它的字线；以及将所有未选位线偏置到地电位。
在两步操作中编程3D RRAM的方法包括：选择要写入的存储单元；将低电压编程脉冲施加到该存储单元中的第一存储电阻器；将高电压编程脉冲施加到该存储单元中的第二存储电阻器；将被选字线设置为地电位；将所有其它字线偏置到0.5VP；用脉冲幅度为-VP的负编程脉冲来偏置第一相关位线；用幅度为+VP的正编程脉冲来偏置第二相关位线；以及用0VP和0.5VP之间的编程电压来脉动所有未选存储电阻器。
通过将小的电压施加到未选位的字线以提高第一相关位线和第二相关位线之间的线电压差；以及将读取电压施加到与被选存储单元相关联的字线并且检测第一相关位线和第二相关位线之间的电压差，读取本发明的存储器单元。
本发明的一个目的是提供可靠的电阻性非易失存储器件，其适合无需有源器件的三维结构的超高密度的存储器阵列。
提供本发明的概述和目的是为了能够很快地理解本发明的本质。通过结合附图来参考本发明优选实施例的详细描述，可以获得对本发明更加彻底的理解。
附图说明
图1是本发明的方法的框图。
图2描述了将CMR存储电阻器编程到高电阻状态的条件。
图3描述了将CMR存储电阻器编程到低电阻状态的条件。
图4描述本发明的三端存储单元。
图5描述了本发明的两端存储单元。
图6是沿着字线的存储器阵列的剖面图。
图7是字线之间截取的存储器阵列的剖面图。
图8是沿着位线的存储器阵列剖面图。
图9是图6-8的3D存储器阵列的单级示意图。
图10是图9的电路的被选位的示意图，其描述了第一最坏情况读取方案。
图11是图9的电路的被选位的示意图，其描述了第二最坏情况读取方案。
图12是描述了最坏情况读取方案的曲线图。
具体实施方式
如先前所述，现有技术的电阻存储器阵列需要有源器件，诸如二极管或晶体管，以防止阵列的存储单元之间相互作用。所以，对于三维阵列来说，每一单元需要通常位于存储器阵列中第一层之上的多晶二极管或晶体管。多晶二极管和多晶晶体管表现出高的漏电流，并且因此不适合结合到大的阵列中。可以使多晶层结晶以提高有源器件的性能并且减少漏电流，然而，结晶需要的高温度处理可能损坏位于该多晶层下面的存储元件。本发明通过提供不需要有源器件的电阻器存储单元来解决上述问题。
现在参考图1，如图1所示的用于制作本发明的器件的步骤通常在10包括：首先根据任何现有技术工艺制备硅基底(12)，以及在该硅基底上制作外围电路(14)。沉积厚度为大约100nm-1000nm的第一氧化硅层并通过化学机械抛光(CMP)处理将其平面化(16)。沉积并蚀刻底部电极(18)，该底部电极具有厚度大约为50nm至300nm的Pt，或者在双层电极中，具有厚度大约为10nm至200nm的TiN以及厚度大约为10nm至100nm的Pt。底部电极的材料可以包括Pt、PtRhOx、PtIrOx以及TiN/Pt。沉积厚度至少为底部电极厚度的1.5倍的第二氧化物层并将其平面化到暴露底部电极的水平(20)。沉积并蚀刻厚度为20nm至150nm的存储电阻器材料，诸如超巨磁阻(CMR)材料或其它合适的存储电阻器材料(22)。沉积Si3N4薄层，该薄层具有例如大约10nm-30nm的厚度(24)。该制作阶段的形成侧壁的可选步骤包括掩模和蚀刻，以在存储电阻器上形成Si3N4侧壁。不管是否形成侧壁，接下来的步骤是沉积厚度为存储电阻器材料厚度1.5倍的第三氧化物层(26)。对该结构进行CMP以便暴露存储电阻器表面。沉积和刻蚀厚度大约为50nm-300nm的Pt顶部电极，或Pt和TiN的双金属顶部电极，其中Pt具有大约为10nm-100nm的厚度，TiN具有大约为10nm-200nm的厚度(28)。顶部电极的材料可以包括Pt、PtRhOx、PtIrOx以及TiN/Pt。沉积和平面化厚度大约为100nm-1000nm的另外的氧化物(30)，之后沉积第二层存储器阵列的底部电极。然后重复所述过程(32)，以完成存储器阵列的第二层和随后的层。理论上，能够在硅表面上制作的存储器阵列的数量没有限制。限制在于硅晶片(silicon wafer)表面上用于感应放大器和外围电路的区域。
如图2和3所示，很明显，编程CMR存储器电阻存在阈值电压。图2描述了将本发明的CMR存储电阻器编程到高电阻状态的条件。当施加的脉冲幅度小于4.5V时，该电阻器的电阻不改变。当施加的脉冲的幅度大于4.5V时，该电阻器的电阻随着脉冲幅度增加而增加。图3描述了将该电阻器的电阻编程到低电阻状态的条件。同样，很明显，对于每一脉冲宽度存在阈值脉冲幅度。高电阻状态和低电阻状态阈值脉冲幅度都随着CMR薄膜厚度的减少而减少。所以，能够选择一个编程脉冲幅度使得在该编程脉冲的二分之一，不管该电阻器处于高电阻状态还是处于低电阻状态，存储电阻器的电阻都不改变。
对于如图4所示的三端存储单元来说，通常在34在底部具有两个电极36、38，在顶部具有一个电极40，在两个底部电极之间施加编程脉冲，顶部电极浮动，例如开路，顶部电极和阴极之间的电阻增加到高电阻状态，同时顶部电极与阳极之间的电阻减小到低电阻状态，其中A是阴极，B是阳极，以及C是地；并且其中R(AC)＝RH且R(BC)＝RL。阈值编程幅度和三端存储电阻器提供了本发明无有源器件的存储单元的基本结构。感应(sensing)、编程以及其它支持电路在硅基底上制作。在两端存储单元的情况下，图5通常在50描述了这种单元，其中地C(52)覆盖在阳极A(54)和阴极B(56)上。
图6-8分别描述了本发明的三维存储器阵列沿着字线、字线之间以及沿着位线的剖面图。虽然所描述的阵列仅有三个垂直叠加的层，但是可以将任何数量的层结合到本发明的存储器阵列中。CMR电阻器用氧化物相隔离。在一些情况中可能需要氧扩散阻挡层，例如Si3N4、Al2O3、TiO2等等。本发明的目标仅在于阵列，因此，在此将不再讨论物理单元结构的细节。
图9描述了一个给定单级存储器阵列的等效电路。其是一个补充输出存储单元阵列。每一存储单元包括两个存储电阻器。每一补充位线连接到差分放大器的相应输入，该差分放大器未在该图中示出。该差分放大器的输出可以用于数字输出“0”或“1”状态连接到反相器。
参考图9，描述编程该阵列的存储器所的两种方法。用于三端存储单元的单步编程方法和适于三端和两端存储单元的两步编程方法。所述单步编程需要RRAM薄膜具有均匀的材料特性。所述两步编程可应用到任何特性非均匀的RRAM薄膜存储单元。
首选讨论单步编程过程。被选择的单元是W2B2，并且第一相关位线B2将被编程到高电压位，第二相关位线 B2将被编程到低电压位。字线W2浮动。用二分之一的编程脉冲电压来偏置所有其它的字线。位线B2接地。编程脉冲VP施加到 B2。所有其它位线偏置到地电位。因此，电阻器R22A处于低电阻状态并且电阻器R22B处于高电阻状态。用编程电压的一半来偏置除了连接到W2字线之外的位2上的所有存储电阻器。所以，没有电阻变化。类似，可以适当地偏置沿着W2的每一位线以每次编程一字。在编程之后，任何给定位内的两个存储单元电阻器分别处于高电阻状态和低电阻状态。
两步编程更加常规。在这个实例中再一次选择单元W2B2。分别将第一被选存储电阻器R22A和存储电阻器R22B编程为低电阻状态和高电阻状态。将被选择的字线W2设置为地电位，并且将所有其它字线偏置到0.5VP。将具有适当脉冲宽度的负编程脉冲和正编程脉冲被分别施加到位线B2和 B2，其中负编程脉冲的脉冲幅度为-VP，正编程脉冲的脉冲幅度为+VP。所述正和负编程脉冲没有必要同时施加，并且可以分开编程A电阻器和B电阻器。所以分别将存储电阻器R22A和R22B编程到低电阻状态RL和高电阻状态RH。所有其它存储电阻器可以用一半的编程脉冲电压来脉动，或者也可以不被脉动。所以，在该编程操作期间，未选择的存储电阻器的电阻将不改变。
通过向字线施加读电压并且检测(读取)共用该存储单元的位线之间的电压差来读取所述存储器阵列。因为未选择位的负载阻抗，给定存储器位的读取输出电压相当复杂，然而，可以将较小的电压施加到未选择的位的字线以提高位线电压差。存在两种极端的情况，这两种情况示于图9和10中，并且允许检测给定存储单元的位线之间的最小差分输出电压。
图10示出了被选位的等效电路，其中将连接到该位线的所有存储电阻器编程为低电阻状态，同时将未连接到该位线的存储电阻器编程为高电阻状态。假设该位线上负载电阻为RO，在该情况中，与被编程为RL的存储电阻器的该位线相关的负载电阻是最小的，并且与RH存储电阻器相关的负载电阻是最大的。所以，希望在不对未选字线施加偏压的情况下，该位线差分输出电压较小。该位线电压是：
V 1 V = 1 - ( R L n + R O - R O V W V ) R L ( R L + R O ) ( R L n + R O ) - R O 2 - - - ( 1 )
以及
V 2 V = 1 - ( R H n + R O - R O V W V ) R H ( R H + R O ) ( R H n + R O ) - R O 2 - - - ( 2 )
现在参考图11，当该给定位线上的被选择存储单元被编程为低电阻状态RL，并且连接到相同位线的所有未选存储单元被编程为RH时，出现第二种情况。图11示出了等效电路。与RL存储电阻器相关联的负载电阻器最大，同时与RH存储电阻器相关联的负载电阻器最小。所以，不对未选字线施加偏压，位线之间的差分电压最大。
V 1 V = 1 - ( R H n + R O - R O V W V ) R L ( R L + R O ) ( R H n + R O ) - R O 2 - - - ( 3 )
和
V 2 V = 1 - ( R L n + R O - R O V W V ) R H ( R H + R O ) ( R L n + R O ) - R O 2 - - - ( 4 )
图12描述了对于具有100个字线连接到给定位线的存储器阵列，构思归一化位线电压作为未选字线偏置电压的函数。高电阻状态是100K欧姆，低电阻状态是1K欧姆。数据表明：位线之间的差分电压，其中VLL(v)和VHH(v)之间的电压差分以及VLH(v)和VHL(v)之间的电压差分分别是图10和11的等效电路的差分输出电压。该差分输出电压随着RH/RL比的增加而增加。
所以，已经公开了3D RRAM。应当理解，在所附权利要求定义的本发明的范围内，可以对其进行进一步的改变和修改。

Claims (7)

1.一种3D RRAM中使用的存储器阵列层，在其上具有外围电路的硅基底上，包括：
沉积和平面化的第一氧化硅层；
采用选自Pt、PtRhOx、PtIrOx以及TiN/Pt组成的材料组中的材料所形成的底部电极；
第二氧化物层，厚度至少为底部电极厚度的1.5倍，被沉积并被平面化到暴露底部电极的水平；
存储电阻器材料层；
Si3N4层；
第三氧化物层，厚度大约为存储电阻器材料厚度的1.5倍；进行CMP以便暴露存储电阻器表面；
采用选自Pt、PtRhOx、PtIrOx以及TiN/Pt组成的材料组中的材料所形成的顶部电极；以及
覆盖氧化物层。
2.权利要求1的存储器阵列层，其中所述第一氧化硅层的厚度大约为100nm至1000nm；其中所述存储电阻器材料的厚度大约为20nm至150nm；所述Si3N4层的厚度大约为10nm至30nm；以及其中所述第三氧化物层的厚度大约为存储电阻器材料厚度的1.5倍。
3.权利要求1的存储器阵列层，其中所述底部电极和顶部电极对于选自Pt、PtRhOx、以及PtIrOx形成的电极组中的电极，厚度大约为50nm至300nm，或者对于双层TiN/Pt，TiN的厚度大约为10nm至200nm并且Pt的厚度为10nm至100nm。
4.一种编程3D RRAM的方法，包括：
选择要写入的存储单元；
将高电压编程脉冲施加到第一相关位线；
将低电压编程脉冲施加到第二相关位线；
浮动关联的字线；
用二分之一的编程脉冲电压来偏置所有其它的字线；以及
将所有未选位线偏置到地电位。
5.权利要求4的方法，其中读取存储单元包括
将小的电压施加到未选位的字线上，以提高第一相关位线和第二相关位线之间的线电压差；以及
将读取电压施加到与被选存储单元相关联的字线，并且检测第一相关位线和第二相关位线之间的电压差。
6.一种编程3D RRAM的方法，包括：
选择要写入的存储单元；
将低电压编程脉冲施加到存储器单元中的第一存储器电阻；
将高电压编程脉冲施加到存储器单元中的第二存储器电阻；
将被选字线设置为地电位；
将所有其它字线偏置到0.5VP；
用脉冲幅度为-VP的负编程脉冲来偏置第一相关位线；
用幅度为+VP的正编程脉冲来偏置第二相关位线；以及
用0VP和0.5VP之间的编程电压来脉动所有未选存储电阻器。
7.权利要求4的方法，其中读取存储单元包括
将小的电压施加到未选字线上，以提高第一相关位线和第二相关位线之间的线电压差；以及
将读取电压施加到与被选存储单元相关联的字线，并且检测第一相关位线和第二相关位线之间的电压差。
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