KR20050050044A - 3d rram - Google Patents
3d rram Download PDFInfo
- Publication number
- KR20050050044A KR20050050044A KR1020040096540A KR20040096540A KR20050050044A KR 20050050044 A KR20050050044 A KR 20050050044A KR 1020040096540 A KR1020040096540 A KR 1020040096540A KR 20040096540 A KR20040096540 A KR 20040096540A KR 20050050044 A KR20050050044 A KR 20050050044A
- Authority
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- South Korea
- Prior art keywords
- thickness
- memory
- bit line
- voltage
- programming
- Prior art date
Links
- 239000000463 material Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 230000008569 process Effects 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 239000007772 electrode material Substances 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- 238000003491 array Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
Abstract
Description
Claims (7)
- 3D RRAM 에 이용하는 메모리 어레이층으로서, 주변 회로를 상부에 갖는 실리콘 기판 상에,증착 및 평탄화되는 제 1 실리콘 산화물층;Pt, PtRhOx, PtIrOx, 및 TiN/Pt 로 이루어지는 재료 그룹으로부터 선택되는 재료로 형성되는 하부 전극;증착된 다음, 상기 하부 전극에서 노출되는 레벨까지 평탄화되는, 상기 하부 전극 두께의 1.5 배 이상의 두께를 갖는 제 2 산화물층;메모리 레지스터 재료층;Si3N4 층;상기 메모리 레지스터 표면이 노출되도록 CMP 되는, 상기 메모리 레지스터 재료 두께의 약 1.5 배의 두께를 갖는 제 3 산화물층;Pt, PtRhOx, PtIrOx, 및 TiN/Pt 로 이루어지는 재료 그룹으로부터 선택되는 재료로 형성되는 상부 전극; 및커버용 산화물층을 포함하는 메모리 어레이층.
- 제 1 항에 있어서,상기 제 1 실리콘 산화물층은 약 100 nm 내지 1000 nm 사이의 두께를 가지며,상기 메모리 레지스터 재료는 약 20 nm 내지 150 nm 사이의 두께를 가지며,상기 Si3N4 층은 약 10 nm 내지 30 nm 사이의 두께를 가지며, 및상기 제 3 산화물층은 상기 메모리 레지스터 재료의 두께의 약 1.5 배의 두께를 갖는 메모리 어레이층.
- 제 1 항에 있어서,상기 하부 전극 및 상기 상부 전극은, Pt, PtRhOx, 및 PtIrOx 로 형성되는 전극 그룹으로부터 선택되는 전극인 경우, 약 50 nm 내지 300 nm 사이의 두께이거나, 또는, 2 층형 TiN/Pt 전극인 경우, TiN 이 약 10 nm 내지 200 nm 사이의 두께 및 Pt 가 약 10 nm 내지 100 nm 사이인 두께를 가지는 메모리 어레이층.
- 기록할 메모리셀을 선택하는 단계,제 1 관련 비트 라인에 고 전압 프로그래밍 펄스를 인가하는 단계,제 2 관련 비트 라인에 저 전압 프로그래밍 펄스를 인가하는 단계,관련되는 워드 라인을 플로팅시키는 단계,나머지 워드 라인 전체를 하프-프로그래밍 (half-programming) 펄스 전압으로 바이어싱 (biasing) 하는 단계, 및선택되지 않은 비트 라인 전체를 접지 전위로 바이어싱하는 단계를 포함하는 3D RRAM 의 프로그래밍 방법.
- 제 4 항에 있어서,메모리셀을 판독하는 단계는,상기 제 1 관련 비트 라인과 상기 제 2 관련 비트 라인 사이의 비트 라인 전압 차이를 증대하기 위하여, 선택되지 않은 비트의 워드 라인에 작은 전압을 인가하는 단계, 및선택되는 메모리셀과 관련되는 워드 라인에 판독 전압을 인가하고, 상기 제 1 관련 비트 라인과 상기 제 2 관련 비트 라인 사이의 전압 차이를 검출하는 단계를 포함하는 3D RRAM 의 프로그래밍 방법.
- 기록할 메모리셀을 선택하는 단계,상기 메모리셀의 제 1 메모리 레지스터에 저 전압 프로그래밍 펄스를 인가하는 단계,상기 메모리셀의 제 2 메모리 레지스터에 고 전압 프로그래밍 펄스를 인가하는 단계,상기 선택되는 워드 라인을 접지 전위로 설정하는 단계,나머지 워드 라인 전체를 0.5 Vp 로 바이어싱하는 단계,-Vp 의 펄스 진폭을 갖는 음의 프로그래밍 펄스로 제 1 관련 비트 라인을 바이어싱하는 단계,+Vp 의 펄스 진폭을 갖는 양의 프로그래밍 펄스로 제 2 관련 비트 라인을 바이어싱하는 단계, 및선택되지 않은 메모리 레지스터 전체를 0 Vp 와 0.5 Vp 사이의 프로그래밍 전압으로 펄싱하는 단계를 포함하는 3D RRAM 의 프로그래밍 방법.
- 제 4 항에 있어서,메모리셀을 판독하는 단계는,상기 제 1 관련 비트 라인과 상기 제 2 관련 비트 라인 사이의 비트 라인 전압 차이를 증대하기 위하여, 선택되지 않은 워드 라인에 작은 전압을 인가하는 단계, 및상기 선택되지 않은 메모리셀과 관련되는 워드 라인에 판독 전압을 인가하고, 상기 제 1 관련 비트 라인과 상기 제 2 관련 비트 라인 사이에 전압 차이를 검출하는 단계를 포함하는 3D RRAM 의 프로그래밍 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/720,890 US7009278B2 (en) | 2003-11-24 | 2003-11-24 | 3d rram |
US10/720,890 | 2003-11-24 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020060057544A Division KR100685701B1 (ko) | 2003-11-24 | 2006-06-26 | 3d rram |
Publications (2)
Publication Number | Publication Date |
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KR20050050044A true KR20050050044A (ko) | 2005-05-27 |
KR100618372B1 KR100618372B1 (ko) | 2006-08-30 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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KR1020040096540A KR100618372B1 (ko) | 2003-11-24 | 2004-11-23 | 3d rram |
KR1020060057544A KR100685701B1 (ko) | 2003-11-24 | 2006-06-26 | 3d rram |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020060057544A KR100685701B1 (ko) | 2003-11-24 | 2006-06-26 | 3d rram |
Country Status (6)
Country | Link |
---|---|
US (2) | US7009278B2 (ko) |
EP (1) | EP1533815A3 (ko) |
JP (2) | JP4986394B2 (ko) |
KR (2) | KR100618372B1 (ko) |
CN (1) | CN100382320C (ko) |
TW (1) | TWI286837B (ko) |
Cited By (2)
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KR100785509B1 (ko) * | 2006-06-19 | 2007-12-13 | 한양대학교 산학협력단 | ReRAM 소자 및 그 제조 방법 |
WO2011096940A1 (en) * | 2010-02-08 | 2011-08-11 | Hewlett-Packard Development Company, L.P. | Memory resistor having multi-layer electrodes |
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KR100785509B1 (ko) * | 2006-06-19 | 2007-12-13 | 한양대학교 산학협력단 | ReRAM 소자 및 그 제조 방법 |
WO2011096940A1 (en) * | 2010-02-08 | 2011-08-11 | Hewlett-Packard Development Company, L.P. | Memory resistor having multi-layer electrodes |
US8737113B2 (en) | 2010-02-08 | 2014-05-27 | Hewlett-Packard Development Company, L.P. | Memory resistor having multi-layer electrodes |
Also Published As
Publication number | Publication date |
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US7342824B2 (en) | 2008-03-11 |
CN100382320C (zh) | 2008-04-16 |
KR100685701B1 (ko) | 2007-02-26 |
TWI286837B (en) | 2007-09-11 |
JP4986394B2 (ja) | 2012-07-25 |
JP2011192380A (ja) | 2011-09-29 |
US20050110117A1 (en) | 2005-05-26 |
JP2005159359A (ja) | 2005-06-16 |
KR100618372B1 (ko) | 2006-08-30 |
US20060033182A1 (en) | 2006-02-16 |
EP1533815A2 (en) | 2005-05-25 |
KR20060084828A (ko) | 2006-07-25 |
JP5216992B2 (ja) | 2013-06-19 |
EP1533815A3 (en) | 2006-07-05 |
TW200539426A (en) | 2005-12-01 |
US7009278B2 (en) | 2006-03-07 |
CN1665030A (zh) | 2005-09-07 |
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