CN1641851A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1641851A
CN1641851A CNA2004100786330A CN200410078633A CN1641851A CN 1641851 A CN1641851 A CN 1641851A CN A2004100786330 A CNA2004100786330 A CN A2004100786330A CN 200410078633 A CN200410078633 A CN 200410078633A CN 1641851 A CN1641851 A CN 1641851A
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China
Prior art keywords
semiconductor chip
mentioned
film
conductive layer
power semiconductor
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Granted
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CNA2004100786330A
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CN100338751C (zh
Inventor
楢崎敦司
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Argona Technology Co ltd
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Mitsubishi Electric Corp
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Publication of CN1641851A publication Critical patent/CN1641851A/zh
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Abstract

提供一种半导体装置，可以简化制造工序。该半导体装置，包括：半导体芯片(1)；在半导体芯片(1)的第1主面上形成的金属层(2b、2c)；在半导体芯片(1)的第2主面上层叠的、由多个导电膜构成的第1导电层(3a)；在第1金属层(2b)上的，从半导体芯片1看，具有与第1导电层(3a)相同顺序的层结构的、由多个层叠的导电膜构成的第2导电层(3b)；以及在金属层(2c)上的，从半导体芯片1看，具有与第1导电层(3a)相同顺序的层结构的、由层叠的多个导电膜构成的第3导电层(3c)。此外，多个导电膜，包括：镍膜(3a2)；以及与半导体芯片的接触电阻比镍膜(3a2)小的低接触电阻导电膜(3a1)。此外，从半导体芯片1的一侧，以低接触电阻导电膜(3a1)和镍膜(3a2)的顺序来形成。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别涉及直接引线键合方式的半导体装置。
背景技术
在现有的电力用半导体装置中，在对电力用半导体芯片进行源极板和漏极板的锡焊时，为了能够利用该锡焊进行接合，在电力用半导体芯片与各电极板之间形成镍膜。
在此，源极板配设在电力用半导体芯片的第1主面侧，漏极板配设在电力用半导体芯片的第2主面侧。此外，作为电力用半导体芯片有MOSFET(金属氧化物半导体场效应晶体管)和IGBT(绝缘栅双极晶体管)等。
不通过导线，把源极板和漏极板直接与在电力用半导体芯片上形成的预定的导电膜(镍膜)接合的方法，称为直接引线键合方式。近年来，为了谋求器件的低电阻化，采用了直接引线键合方式。
此外，通常在电力用半导体芯片的第1主面侧形成预定的图形。为了保护该图形免受外力，在电力用半导体芯片的第1主面与镍膜之间形成铝-硅等金属层。
由于在电力用半导体芯片的第2主面侧对该第2主面直接形成镍膜，产生了在电力用半导体芯片与镍膜之间的接触电阻变大的问题。
因此，在第2主面侧，在电力用半导体芯片与镍膜之间，形成了与电力用半导体芯片的接触电阻小的导电膜(下面，称为低接触电阻导电膜)。
但是，当对该电力用半导体装置施行热处理时，在镍膜和低接触电阻导电膜上产生横向应力。镍膜和低接触电阻导电膜的热膨胀率导致该横向应力的产生。
但是，如上所述，如果只在电力用半导体芯片的第2主侧面上形成低接触电阻导电膜，在第1主面侧形成的镍膜所导致的横向应力、与在第2主面侧形成的镍膜和低接触电阻导电膜所导致的横向应力之间，产生了差别。由于该横向应力之差，电力用半导体芯片产生了翘曲的问题，在第1主面侧形成凸面。
以减轻该半导体芯片的翘曲为目的，在第1主面侧也在镍膜与电力用半导体芯片上的金属层之间形成了在第2主面侧追加的低接触电阻导电膜。即，从电力用半导体芯片看，在电力用半导体芯片的第2主面侧形成的导电膜的层结构与在第1主面侧形成的导电膜的层结构是相同的结构。
除了源极板以外，还把铝导线的一端引线键合到电力用半导体芯片的第1主面侧。然后，把该铝导线的另一端与栅极连接。
作为与上述电力用半导体装置的结构有关的现有文献，有例如在专利文献1、2中公开的文献。
<专利文献1>日本特开2002-198515号公报(图2)。
<专利文献2>日本特开2003-243585号公报(图1)。
在上述现有技术的电力用半导体装置中，利用焊锡接合源极板的处理和铝导线的引线键合处理必须通过单独的工序进行，成为制造工序烦杂的主要原因。
在现有技术的电力用半导体装置中，在电力用半导体芯片的第1主面的一部分中还有未形成上述层结构的导电膜的部位(对铝导线进行引线键合的部位)。因此，在现有技术的电力用半导体装置中，不能充分减轻电力用半导体芯片的翘曲。
发明内容
因此，本发明的目的在于，提供能够伴随着谋求简化制造工序，更好地抑制电力用半导体芯片翘曲的电力用半导体装置。
为了达到上述目的，本发明的一种半导体装置，其特征在于包括：半导体芯片；在上述半导体芯片的第1主面上形成的第1、第2金属层；在上述半导体芯片的第2主面上层叠的、由多个导电膜构成的第1导电层；在上述第1金属层上的，从上述半导体芯片看，具有与上述第1导电层相同顺序的层结构的、由层叠的多个导电膜构成的第2导电层；以及在上述第2金属层上的，从上述半导体芯片看，具有与上述第1导电层相同顺序的层结构的、由层叠的多个导电膜构成的第3导电层，上述多个导电膜包括：镍膜；以及与上述半导体芯片的接触电阻比上述镍膜与上述半导体芯片的接触电阻小的低接触电阻导电膜，且从上述半导体芯片的一侧，以上述低接触电阻导电膜和上述镍膜的顺序来形成上述多个导电膜。
由于本发明的半导体装置，其特征在于包括：半导体芯片；在上述半导体芯片的第1主面上形成的第1、第2金属层；在上述半导体芯片的第2主面上层叠的、由多个导电膜构成的第1导电层；在上述第1金属层上的，从上述半导体芯片看，具有与上述第1导电层相同顺序的层结构的、由层叠的多个导电膜构成的第2导电层；以及在上述第2金属层上的，从上述半导体芯片看，具有与上述第1导电层相同顺序的层结构的、由层叠的多个导电膜构成的第3导电导层，上述多个导电膜包括：镍膜；以及与上述半导体芯片的接触电阻比上述镍膜小的低接触电阻导电膜，从上述半导体芯片的一侧，以上述低接触电阻导电膜和上述镍膜的顺序来形成，所以在各导电层上能够利用焊锡与电极板接合。因此，能够通过同一个工序同时直接线线键合全部电极板。因此，可以谋求简化制造工序。由于能够不通过铝导线等直接把全部电极板与器件连接，还可以谋求降低半导体装置工作时的能耗量。由于不使用强度低的铝导线而直接配设强度高的板状电极板，还能够消除被看作问题的铝导线断路等的电气不合格。由于第3导电层的层结构，从电力用半导体芯片看，具有与第1导电层相同的层结构，故通过设置第3导电层还能够比现有更好地抑制半导体芯片的翘曲。
附图说明
图1为示出本发明的电力用半导体装置的概略结构的剖面图。
图2为示出实施方式1的电力用半导体装置的一部分的剖面图。
图3为示出实施方式1的电力用半导体装置的一部分的剖面图。
图4为示出实施方式2的电力用半导体装置的一部分的剖面图。
图5为示出实施方式2的电力用半导体装置的一部分的剖面图。
图6为示出实施方式3的电力用半导体装置的一部分的剖面图。
图7为示出实施方式3的电力用半导体装置的一部分的剖面图。
具体实施方式
下面，基于示出其实施方式的附图，具体地说明本发明。
<实施方式1>
图1示出本实施方式的电力用半导体装置的剖面图。在此，图1中为了方便展示而省略了封装、该封装内的各端子和第1主电极板(漏极板)下部的绝缘基板等。
如图1所示，在电力用半导体芯片1的第2主面(图1中，电力用半导体芯片1的下表面)上，形成了第1导电层3a。第1导电层3a还通过焊锡10与第1主电极板(漏极板)6接合。该接合通过直接引线键合方式进行。
在此，第1导电层3a具有由多个导电膜构成的层叠结构。此外，第1主电极板6由例如Cu等构成。
此外，虽未图示，但在电力用半导体芯片1的第1主面(图1中，电力用半导体芯片1的上表面)上形成了预定的图形。在此，作为电力用半导体芯片1，例如有IGBT(绝缘栅双极晶体管)或二极管等。还对第2主面施行研磨处理，直到电力用半导体芯片1成为预定的厚度(例如，约200μm)。
如图1所示，还在电力用半导体芯片1的第1主面上形成了两个金属层2b、2c。为了保护在电力用半导体芯片的第1主面上形成的图形免受外力，即作为对图形进行保护的缓冲材料，设置了该金属层2b、2c。
在此，金属层2b、2c，相互电气分离。此外，金属层2b、2c为铝-硅等的金属层。
此外，如图1所示，在一个金属层2b上形成了第2导电层3b。与此不同，在另一个金属层2c上形成了第3导电层3c。在此，第2导电层3b和第3导电层3c都具有由多个导电膜构成的层叠结构。而且，第2导电层3b和第3导电层3c，从电力用半导体芯片1看，都具有与第1导电层3a相同顺序的层结构。
在此，也可以是，不仅各导电膜的顺序相同，而且各导电膜的膜厚也相同。即，也可以是，构成第2导电层3b和第3导电层3c的各导电膜的膜厚、与和该各导电膜对应的第1导电层3a的导电膜的膜厚相同。
此外，如图1所示，在第2导电层3b上配设第2主电极板(源极板)4，在第3导电层3c上配设控制极板(栅极板)5。
在此，第2主电极板4通过焊锡10与第2导电层3b接合，控制极板5通过焊锡10与第3导电层3c接合。该接合通过直接引线键合方式进行。此外，第2主电极板4和控制极板5由例如Cu等构成。
接着，基于图2所示的剖面图，说明各导电层3a、3b的具体层结构。在此，图2为把图1的虚线7的区域放大后的剖面图。
如图2所示，第1导电层3a和第2导电层3b都具有由多个导电膜构成的层叠结构。在此，各导电膜通过例如溅射法、蒸镀法、或电镀法形成。
第1导电层3a具有把低接触电阻导电膜3a1和镍膜3a2对第2主面以该顺序层叠的层结构。
在此，所谓低接触电阻导电膜3a1，是与电力用半导体芯片1的接触电阻小的导电膜。低接触电阻导电膜3a1与电力用半导体芯片1的接触电阻，比镍膜3a2与电力用半导体芯片1的接触电阻小。此外，低接触电阻导电膜3a1，与电力用半导体芯片1的第2主面接触而形成。此外，镍膜3a2是用于能够利用焊锡10与第1主电极6接合的导电膜。
此外，如图2所示，以减轻电力用半导体芯片1的翘曲为目的，在金属膜2b上形成了从电力用半导体芯片1看，具有与第1导电层3a相同顺序(在此，也可以如上所述，对应的导电膜相互间的膜厚相同)的层结构的第2导电层3b。
即，第2导电层3b从电力用半导体芯片1看，具有低接触电阻导电膜3b1和镍膜3b2以该顺序层叠而成的层结构。镍膜3b2从电力用半导体芯片1看，存在于最外侧，通过该镍膜3b2能够利用焊锡10与第2主电极4接合。
再有，为了防止该镍膜3a2、3b2的氧化，在镍膜3a2、3b2与焊锡10之间形成膜厚约200nm的金膜，但在进行与主电极板4、6的接合处理时，金膜溶解，作为金膜的实体消失了。
接着，基于图3所示的剖面图，说明导电层3c的具体层结构。在此，图3为把图1的虚线8的区域放大后的剖面图。
如图3所示，第3导电层3c具有由多个导电膜构成的层叠结构。在此，各导电膜通过例如溅射法、蒸镀法、或电镀法形成。
由于第1导电层3a的结构与图2相同，故在此省略了具体说明。
如图3所示，以进一步减轻电力用半导体芯片1的翘曲为目的，在金属膜2c上形成了从电力用半导体芯片1看，具有与第1导电层3a相同顺序(在此，也可以如上所述，对应的导电膜相互间的膜厚相同)的层结构的第3导电层3c。
即，第3导电层3c从电力用半导体芯片1看，具有低接触电阻导电膜3c1和镍膜3c2以该顺序层叠而成的层结构。镍膜3c2从电力用半导体芯片1看，存在于最外侧，通过该镍膜3c2能够利用焊锡10与控制极5接合。
再有，为了防止该镍膜3c2的氧化，在镍膜3c2与焊锡10之间形成膜厚约200nm的金膜，但在进行与控制极板5的接合处理时，金膜溶解，作为金膜的实体消失了。
如从图1、3可看到的那样，在本实施方式的电力用半导体装置中，在电力用半导体芯片1的第1主面侧形成了从电力用半导体芯片1看在最外侧具有镍膜3c2的第3导电层3c。由此，能够通过直接引线键合方式利用焊锡10与控制极板5接合。
因此，能够利用同一个工序通过焊锡10接合第2主电极板4、控制极板5，即能够同时对第2主电极板4和控制极板5进行直接线线键合。因此，可以谋求简化制造工序。
由于不通过铝导线等直接把控制极板5与器件连接，故还可以谋求降低该电力用半导体装置工作时的能耗量。
由于不使用强度低的铝导线而直接配设强度高的板状的控制极板5，故还能够消除被看作问题的铝导线断路等的电气不合格。
而且，由于第3导电层3c的层结构，从电力用半导体芯片1看，具有与第1导电层3a相同顺序(在此，也可以如上所述，对应的导电膜相互间的膜厚相同)的层结构，故通过设置该第3导电层3c还能够进一步抑制电力用半导体芯片1的翘曲。
即，当对电力用半导体装置进行热处理等时，在电力用半导体芯片1的第2主面侧生成第1导电层3a所导致的横向应力，在第1主面侧生成第2和第3导电层3b、3c所导致的横向应力。
但是，由于第3导电层3c具有上述层结构，故通过设置该第3导电层3c能够更加减小上述两个横向应力之差。
因此，通过设置该第3导电层3c，能够比现有技术的电力用半导体装置(没有第3导层电3c的电力用半导体装置)更好地抑制电力用半导体芯片1的第1主面侧形成凸面状的翘曲。
此外，在上述中，对于是单层的情况描述了铝-硅金属层2b、2c，但是，也可以是多层化来谋求增大膜厚。金属层2b、2c还起到作为抑制电力用半导体芯片1翘曲的增强件的作用，通过使该金属层2b、2c膜厚增大能够更加减轻电力用半导体芯片1的翘曲。
<实施方式2>
图4和图5示出本实施方式的电力用半导体装置。图4为在本实施方式的电力用半导体装置中，把图1的虚线7的区域放大后的剖面图。此外，图5为在本实施方式的电力用半导体装置中，把图1的虚线8的区域放大后的剖面图。
首先，说明图4所示的结构。
如图4所示，在电力用半导体芯片1的第2主面的表面内，形成了N型杂质区1a。在此，N型杂质区的杂质浓度为大于等于1×1019。
此外，在电力用半导体芯片1的第2主面侧形成的第1导电层3a，如图4所示，由钛膜3a1和镍膜3a2构成。即，作为低接触电阻导电膜采用钛膜3a1。
在此，钛膜3a1在电力用半导体芯片1的第2主面上形成。而且，镍膜3a2在钛膜3a1上形成。钛膜3a1的膜厚约为30nm。镍膜3a1的膜厚约为200nm。
再有，为了防止该镍膜3a2的氧化，在镍膜3a2与焊锡10之间形成膜厚约400nm的金膜，但在进行与第1主电极板6的接合处理时，但在进行与第1主电极板6的接合处理时，金膜溶解，作为金膜的实体消失了。
此外，如图4所示，在电力用半导体芯片1的第1主面上形成了金属层2b。然后，在金属层2b上形成了从电力用半导体芯片1看，具有与第1导电层3a相同顺序(在此，也可以与实施方式1一样，对应的导电膜相互间的膜厚相同)的层结构的第2导电层3b。
即，第2导电层3b由在金属层2b上形成的钛膜3b1和在该钛膜3b1上形成的镍膜3b2构成。各导电膜3b1、3b2的膜厚也与第1导电层3a的对应导电膜相同。
再有，为了防止该镍膜3b2的氧化，在镍膜3b2与焊锡10之间形成膜厚约400nm的金膜，但在进行与第2主电极板4的接合处理时，金膜溶解，作为金膜的实体消失了。
接着，说明图5所示的结构。
如图5所示，在电力用半导体芯片1的第2主面的表面内，如用图4说明了的那样，形成了N型杂质区1a。
此外，在电力用半导体芯片1的第2主面侧形成的第1导电层3a的结构与图4相同。
此外，如图5所示，在电力用半导体芯片1的第1主面上形成了金属层2c。然后，在金属层2c上形成了从电力用半导体芯片1看，具有与第1导电层3a相同顺序(在此，也可以如上所述，对应的导电膜相互间的膜厚相同)的层结构的第3导电层3c。
即，第3导电层3c由在金属层2c上形成的钛膜3c1和在该钛膜3c1上形成的镍膜3c2构成。各导电膜3c1、3c2的膜厚也与第1导电层3a的对应导电膜相同。
再有，为了防止该镍膜3c2的氧化。在镍膜3c2与焊锡10之间形成膜厚约400nm的金膜，但在进行与控制极板5的接合处理时，金膜溶解，作为金膜的实体消失了。
在本实施方式的电力用半导体装置中，由于作为与在电力用半导体芯片1上形成的N型杂质区1a接触的低接触电阻导电膜采用了与N型杂质区1a的接触电阻小的钛膜3a1，故能够把电力用半导体芯片1与钛膜3a1之间的接触电阻抑制到更小。
在本实施方式中，当然也与实施方式1一样，具有更加减轻电力用半导体芯片1的翘曲的效果。
<实施方式3>
图6和图7示出本实施方式的电力用半导体装置。图6为在本实施方式的电力用半导体装置中，把图1的虚线7的区域放大后的剖面图。此外，图7为在本实施方式的电力用半导体装置中，把图1的虚线8的区域放大后的剖面图。
首先，说明图6所示的结构。
如图6所示，在电力用半导体芯片1的第2主面的表面内，形成了P型杂质区1b。在此，P型杂质区的杂质浓度为大于等于1×1019。
此外，在电力用半导体芯片1的第2主面侧形成的第1导电层3a，如图6所示，由铝膜3a1s、钼膜3a1t和镍膜3a2构成。即，作为低接触电阻导电膜3a1采用铝膜3a1s、钼膜3a1t。
在此，铝膜3a1s在电力用半导体芯片1的第2主面上形成。此外，钼膜3a1t在铝膜3a1s上形成。进而，镍膜3a2在钼膜3a1t上形成。铝膜3a1的膜厚约为800nm。钼膜3a1t的膜厚约为180nm，而镍膜3a2的膜厚约为300nm。
再有，为了防止该镍膜3a2的氧化，在镍膜3a2与焊锡10之间形成膜厚约200nm的金膜，但在进行与第1主电极6的接合处理时，金膜溶解，作为金膜的实体消失了。
此外，如图6所示，在电力用半导体芯片1的第1主面上形成了金属层2b。然后，在金属层2b上形成了从电力用半导体芯片1看，具有与第1导电层3a相同顺序(在此，也可以与实施方式1一样，对应的导电膜相互间的膜原相同)的层结构的第2导电层3b。
即，第2导电层3b由在金属层2b上形成的铝膜3b1s、在该铝膜3b1s上形成的钼膜3b1t和在该钼膜3b1t上形成的镍膜3b2构成。各导电膜3b1s、3b1t、3b2的膜厚与第1导电层3a的对应导电膜相同。
再有，为了防止该镍膜3b2的氧化，在镍膜3b2与焊锡10之间形成膜厚约200nm的金膜，但在进行与第2主电极板4的接合处理时，金膜溶解，作为金膜的实体消失了。
接着，说明图7所示的结构。
如图7所示，在电力用半导体芯片1的第2主面的表面内，如用图6说明了的那样，形成了P型杂质区1b。
此外，在电力用半导体芯片1的第2主面侧形成的第1导电层3a的结构与图6相同。
此外，如图7所示，在电力用半导体芯片1的第1主面上形成了金属层2c。然后，在金属层2c上形成了从半导体芯片1看，具有与第1导电层3a相同顺序(在此，也可以如上所述，对应的导电膜相互间的膜厚相同)的层结构的第3层导电层3c。
即，第3导电层3c由在金属层2c上形成的铝膜3c1s、在该铝膜3c1s上形成的钼膜3c1t和在该钼膜3c1t上形成的镍膜3c2构成。各导电膜3c1s、3c1t、3c2的膜厚也与第1导电层3a的对应导电膜相同。
再有，为了防止该镍膜3c2的氧化，在镍膜3c2与焊锡10之间形成膜厚约200nm的金膜，但在进行与控制极板5的结合处理时，金膜溶解，作为金膜的实体消失了。
在本实施方式的电力用半导体装置中，由于作为与在电力用半导体芯片1上形成的P型杂质区1b接触的低接触电阻导电膜，采用了由与P型杂质区1b的接触电阻小的铝膜和钼膜构成的层叠膜，故能够把电力用半导体芯片1与该层叠膜之间的接触电阻抑制得更小。
在本实施方式中，当然也与实施方式1一样，具有更加减轻电力用半导体芯片1的翘曲的效果。
<实施方式4>
在本实施方式的电力用半导体装置中，在电力用半导体芯片1的第1主面上形成的金属层2b、2c包含下面的金属元素。即，包含与和金属层2b、2c相接的部分上的低接触电阻导电膜3a1、3b1、3c1相同的金属元素。
例如，在实施方式3的电力用半导体装置中，在构成低接触电阻导电膜3a1、3b1、3c1的导电膜中，与金属层2b、2c接触的导电膜的金属元素为铝(参照图6、7)。因此，作为金属层2b、2c，构成为包含该铝。
通过作成上述那样的结构，能够降低金属层2b、2c与低接触电阻导电膜3a1、3b1、3c1之间的势垒。因此，能够进一步降低在金属层2b、2c与低接触电阻导电膜3a1、3b1、3c1之间的接触电阻。
再有，在上述各实施方式中，作为电力用半导体芯片1可以采用IGBT、MOSFET(金属氧化物半导体场效应晶体管)、二极管(在二极管的情况下，由于控制极不存在，故存在于该控制极上的金属层也不存在)、或闸流管等。
尤其在作为电力用半导体芯片1采用了IGBT时，具有下面示出的效果。
即，迄今在IGBT中，在通过引线键合方式把布线接合到控制极上时，由于接合部发热而存在着该接合部的电阻增大的问题。
但是，在本发明的电力用半导体装置中，由于利用直接引线键合方式，不通过布线而直接对IGBT配设控制极板，故能够消除在IGBT与布线的结合部中的、发热所引起的电阻增大的问题。
此外，在各实施方式的发明中，谈到电力用半导体芯片1为单体的情况。但是，也可以把由多个电力用半导体芯片1构成的HVIC(高压集成电路)与单体电力用半导体芯片1置换而应用上述各实施方式。
不限于电力用半导体芯片1，还可以对电力用以外的半导体芯片应用上述各实施方式。进而，对于由多个半导体芯片构成的LSI(大规模集成电路)也可以应用上述各实施方式。

Claims (6)

1.一种半导体装置，其特征在于包括：
半导体芯片；
在上述半导体芯片的第1主面上形成的第1、第2金属层；
在上述半导体芯片的第2主面上层叠的、由多个导电膜构成的第1导电层；
在上述第1金属层上的，从上述半导体芯片看，具有与上述第1导电层相同顺序的层结构的、由层叠的多个导电膜构成的第2导电层；以及
在上述第2金属层上的，从上述半导体芯片看，具有与上述第1导电层相同顺序的层结构的、由层叠的多个导电膜构成的第3导电层，
上述多个导电膜包括：镍膜；以及与上述半导体芯片的接触电阻比上述镍膜与上述半导体芯片的接触电阻小的低接触电阻导电膜，且
从上述半导体芯片的一侧，以上述低接触电阻导电膜和上述镍膜的顺序来形成上述多个导电膜。
2.根据权利要求1所述的半导体装置，其特征在于还包括：
在上述第1～第3导电层上，分别夹着焊锡配设的第1～第3电极板。
3.根据权利要求1或权利要求2所述的半导体装置，其特征在于，
上述半导体芯片具有在上述第2主面的表面内形成的N型杂质区，
上述低接触电阻导电膜为钛膜。
4.根据权利要求1或权利要求2所述的半导体装置，其特征在于，
上述半导体芯片具有在上述第2主面的表面内形成的P型杂质区，
上述低接触电阻导电膜为，从上述半导体芯片看，铝膜和钼膜以该顺序层叠而成的膜。
5.根据权利要求1或权利要求2所述的半导体装置，其特征在于，
上述第1、第2金属层包含与和它们自身相接的部分上的上述低接触电阻导电膜相同的金属元素。
6.根据权利要求1或权利要求2所述的半导体装置，其特征在于，
上述半导体芯片为绝缘栅型晶体管。
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